AT91SAM7

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This article describes device specifics of the Atmel AT91SAM7 series devices.

Reset strategy

The reset pin of the device is per default disabled. This means that the reset strategies which rely on the reset pin (low pulse on reset) do not work per default. For this reason a special reset strategy has been made available.

It is recommended to use this reset strategy. This special reset strategy resets the peripherals by writing to the RSTC_CR register. Resetting the peripherals puts all peripherals in the defined reset state. This includes memory mapping register, which means that after reset flash is mapped to address 0. It is also possible to achieve the same effect by writing 0x4 to the RSTC_CR register located at address 0xfffffd00.

This information is applicable to the following devices:

  • AT91SAM7S (all devices)
  • AT91SAM7SE (all devices)
  • AT91SAM7X (all devices)
  • AT91SAM7XC (all devices)
  • AT91SAM7A (all devices)

Memory mapping

Either flash or RAM can be mapped to address 0. After reset flash is mapped to address 0. In order to majlink_supported_devices.html RAM to address 0, a 1 can be written to the RSTC_CR register. Unfortunately, this remap register is a toggle register, which switches between RAM and flash every time bit zero is written.

In order to achieve a defined mapping, there are two options:

  1. Use the software reset described above.
  2. Test if RAM is located at 0 using multiple read/write operations and testing the results.

Clearly 1. is the easiest solution and is recommended.

This information is applicable to the following devices:

  • AT91SAM7S (all devices)
  • AT91SAM7SE (all devices)
  • AT91SAM7X (all devices)
  • AT91SAM7XC (all devices)
  • AT91SAM7A (all devices)

Recommended init sequence

In order to work with an ATMEL AT91SAM7 device, it has to be initialized. The following paragraph describes the steps of an init sequence. An example for different software tools, such as J-Link GDB Server, IAR Workbench and RDI, is given.

  • Set JTAG speed to 30kHz.
  • Reset target.
  • Perform peripheral reset.
  • Disable watchdog.
  • Initialize PLL.
  • Use full JTAG speed.

Samples

GDB Sample

# connect to the J-Link gdb server
target remote localhost:2331
monitor flash device = AT91SAM7S256
monitor flash download = 1
monitor flash breakpoints = 1
# Set JTAG speed to 30 kHz
monitor endian little
monitor speed 30
# Reset the target
monitor reset 8
monitor sleep 10
# Perform peripheral reset
monitor long 0xFFFFFD00 = 0xA5000004
monitor sleep 10
# Disable watchdog
monitor long 0xFFFFFD44 = 0x00008000
monitor sleep 10
# Initialize PLL
monitor long 0xFFFFFC20 = 0x00000601
monitor sleep 10
monitor long 0xFFFFFC2C = 0x00480a0e
monitor sleep 10
monitor long 0xFFFFFC30 = 0x00000007
monitor sleep 10
monitor long 0xFFFFFF60 = 0x00480100
monitor sleep 100
monitor speed 12000
break main
load continue

IAR Sample

/*******************************************************************
*
*        _Init()
*/
_Init() {
  __emulatorSpeed(30000);                          // Set JTAG speed to 30 kHz
  __writeMemory32(0xA5000004,0xFFFFFD00,"Memory"); // Perform peripheral reset
  __sleep(20000); 
  __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); // Disable Watchdog
  __sleep(20000); 
  __writeMemory32(0x00000601,0xFFFFFC20,"Memory"); // PLL
  __sleep(20000); 
  __writeMemory32(0x10191c05,0xFFFFFC2C,"Memory"); // PLL 
  __sleep(20000);
  __writeMemory32(0x00000007,0xFFFFFC30,"Memory"); // PLL 
  __sleep(20000);
  __writeMemory32(0x002f0100,0xFFFFFF60,"Memory"); // Set 1 wait state for 
  __sleep(20000);                                  // flash (2 cycles) 
  __emulatorSpeed(12000000);                       // Use full JTAG speed 
} 

/*******************************************************************
*
*        execUserReset()
*/ 
execUserReset() { 
  __message "execUserReset()";
  _Init(); 
} 

/******************************************************************* 
* 
*        execUserPreload()
*/
execUserPreload() { 
  __message "execUserPreload()"; 
  _Init(); 
}