Arm trace technical specification
When using the J-Trace PRO as a debugging tool it is crucial for a successful session that the trace data output by the microcontroller is meeting specific timing requirements. The trace clock speed (TRACECLK) is on most microcontrollers directly dependent on the CPU clock speed and is usually half of the CPU clock speed. The following article will show the Arm trace timing requirements and which Arm Coresight components are required for which type of instruction tracing.
Arm trace timing requirements
Arm defines the trace timing requirements as follows:
|twl||TRACECLK LOW pulse width||Min. 2 ns|
|twh||TRACECLK HIGH pulse width||Min. 2 ns|
|tr/tf||Clock and data rise/fall time||Max. 3 ns|
|ts||Data setup time||Min. 3 ns|
|th||Data hold time||Min. 2 ns|
Note: J-Trace PRO has been designed to work with min. 1 ns ts and min. 1 ns th.
According to specification the maximum in spec trace clock is 100 MHz. But as there are some target devices that support even higher trace clock signals than that J-Trace Pro also supports higher trace clock speeds as explained in the note above.
Solution for out of spec signals
In some rare cases devices supporting Embedded Trace Macrocell (ETM) trace are not outputting signals that fulfill the aforementioned timing requirements. To still make trace debugging available to the customer the J-Trace PRO has a so called Trace timing configuration feature which compensates wrongly output trace data signals.