Arria 10 SoC Development Kit

From SEGGER Wiki
Jump to navigation Jump to search

Connecting J-Link to Altera Arria 10 SoC Development Kit

For connecting J-Link with the Altera Arria 10 Cortex-A9 the debug interface signal lines need to be connected to the JTAG connector(J24) on the board, so that the onboard debugger cannot change pin states while the J-Link communicates with the target.

Here is the pin config between JTAG connector(J24) on the evalboard and the J-Link debug emulator:

JTAG(J24)          J-Link
1  (TCK)     <-->  9  (TCK)
2  (ENABLEN) <-->  6  (GND)
3  (TCK)     <-->  13 (TDO)
4  (3V3)     <-->  1  (VTref)
5  (TMS)     <-->  7  (TMS)
6  (RSTn)    <-->  15 (RESET)
9  (TDI)     <-->  5  (TDI)
10 (GND)     <-->  4  (GND)

Deviating from the default settings SW3 on the evalboard needs the following setting, so only the Arria 10 device is in the JTAG chain:

SW3
1  (Arria 10)  -->  OFF (default) Arria10 JTAG Enable
2  (I/O MAX V) -->  ON  (changed) MAXV JTAG Bypass
3  (FMCA)      -->  ON  (default) FMCA JTAG Bypass
4  (FMCB)      -->  ON  (default) FMCB JTAG Bypass
5  (PCIe)      -->  ON  (default) PCIe JTAG Bypass
6  (MSTR[0])   -->  OFF (default)
7  (MSTR[1])   -->  OFF (default)
8  (MSTR[2])   -->  OFF (default)

A successful connection should look like this:

Altera Arria 10 J-Link.png