I.MXRT1060

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Flash Programming

NXP's iMXRT105x family features a Cortex-M7 core without internal flash but with support for QSPI and HyperFlash through a so called FLEXSPI controller. NXP's official evaluation board, the MIMXRT1050 EVK is shipped with a 512Mbit Hyper Flash device by default. Alternatively, a QSPI flash can be mounted but several board modifications (removing the hyper flash, adding resistors, etc...) are required. As both flashes are accessed through the same memory mapped address space, either the HyperFlash or the QSPI flash RAMCode needs to be used for memory accesses to this area. Please find below further information how to enable the desired flash algorithm (RAMCode). Official flash programming support has been added in J-Link software version V6.31d.

Minimum requirements

  • Min. J-Link software version V6.40 (release) is required. Later versions will also work. Earlier versions do not support flash programming on this device.

Enable Flashloader

QSPI Flash

By default, the QSPI Flash algorithm is selected in the J-Link software. No additional steps are required.

Hyper Flash

To enable the Hyperflash support in the J-Link software, the JLinkDevices.xml needs to be modified. For further information regarding the JLinkDevices.xml, please refer to the Open Flashloader chapter in the J-Link User Manual (UM08001).

  1. Open the JLinkDevices.xml (e.g. C:\Program Files (x86)\SEGGER\JLink_V640\JLinkDevices.xml
  2. Search the desired iMXRT <Device> entry
  3. Change Loader="Devices/NXP/iMXRT106x/NXP_iMXRT106x_QSPI.elf" to Loader="Devices/NXP/iMXRT105x/NXP_iMXRT105x_HyperFlash.elf" Yes you need to select the HyperFlash Loader from iMXRT105x, iMXRT105x and iMXRT106x use the same Hyperflash configuration.
  4. Save the JLinkDevices.xml

From now, the J-Link software uses the HyperFlash RAMCode instead of the QSPI RAMCode for the flash download.

NOTE: Please note that several hardware modifications needs to be done on the evaluation board to enable Hyperflash programming / booting from Hyperflash. For further information regarding this, please refer to NXPs board user manual.