Infineon CYT2BL

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CYT2BL (TVII-B-E-4M) is a subfamily of Traveo II microcontrollers containing a Cortex M4 and Cortex M0+ CPU.


The CYT2BL family features 2 x 256 KB = 512 KB of SRAM located at 0x08000000. The first 2 KB are reserved for internal usage and may not be used.

Flash memory layout

The CYT2BL series devices have 4160 KiB Code flash and a 128 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.

Flash Start adress End adress Sector size Sector count Total size
Code flash large area 0x10000000 0x103EFFFF 32 KiB 126 4032 KiB
Code flash small area 0x103F0000 0x1040FFFF 8 KiB 16 128 KiB
Work flash large area 0x14000000 0x14017FFF 2 KiB 48 96 KiB
Work flash small area 0x14018000 0x1401FFFF 128 B 256 32 KiB