J-Link Cortex-M application uses cycle counter
The ARM Cortex-M cores provide a cycle counter as part of the Data Watchpoint and Trace unit (DWT) which is a debug unit of the Cortex-M cores.
There are certain circumstances where it might make sense for the target application to make use of the cycle counter to time certain application specific steps. This might interfere with the J-Link logic on debug session close because by default J-Link clears all debug enable bits (e.g. the DEMCR.TRCENA which enables/disables the ITM and DWT units of the Cortex-M core). J-Link needs to clear all debug bits on debug session close to make sure that the WFI / WFE instructions enter low power modes correctly and do not leave certain clocks enabled which would result in a higher power consumption of the chip.
If usage of the cycle counter in the target application is absolutely necessary, J-Link can be configured to not clear the debug bits on debug session close.