J-Link NEORV32

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The NEORV32 is an free and open-source RV32 based RISC-V CPU that is supported by J-Link. In addition to this article, the generic RISC-V specifics apply. See separate wiki article

Eval board

There is currently (December 2021) no out-of-the-box eval board available with this core.
However, there is an affordable FPGA maker board and a good tutorial from emb4fun available to get the NEORV32 running on hardware: Tutorial

JTAG speed

  • The JTAG speed used must not exceed 1/5 of the current CPU speed of the NEORV32.
  • Up to version (22nd November 2021) the JTAG interface of the NEORV32 was not JTAG compliant and changed the data on the wrong edge of TCK.
    This could cause problems when using JTAG speeds of 4 MHz and higher.

RTT support

Unfortunately, the NEORV32 does not support system bus access and therefore does not have RTT support.