The LPC54xx series devices are flashless Cortex-M4 based IoT devices. They always boot from external memory (usually QSPI flash).
For power saving reasons, the SRAM is devided in sections (SRAM0 - SRAM3), which can be clocked and powered separately. By default (after reset), only SRAM0 is clocked and powered. Clocks and power of the separate SRAM sections can be controlled via the AHB Clock Control register 0 and the Power Configuration register 0.
As not all RAM is available by default, only the default SRAM section (SRAM0) is searched for the RTT Control Block. However, the other RAM sections can be added as search ranges by the user via the methods explained in the RTT article > Troubleshooting section.