Memory accesses

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Modes when accessing memory while CPU is running

Memory on the target device can be accessed in different modes. Some modes are not available on all devices. The modes only matter in case a memory access is performed while the target CPU is running.

Memory can be accessed in the following modes:

  • Background mode
  • Stop mode
  • Legacy stop mode

Background mode

In this mode, J-Link can access the memory of the target system while the MCU + application keeps running (background memory access), effectively not impacting the real time behavior of the application.

Cores with background mode support

  • Cortex-M based devices (all cores from the series)
  • Renesas RX based devices (all cores from the series)

J-Links with background mode support

  • All that support the cores listed above. More...

Stop mode

In this mode, J-Link temporarily halts the CPU (interrupts the execution of the target application) to access the memory and continues operation automatically after the memory access is done. The actual impact (halted time) on the real time behavior depends on the setup (target interface speed used, target interface used, length of JTAG chain, actual core that is used, ...).

Note: The whole operation (halt + acc + go) is performed inside the J-Link firmware, reducing the halted time of the CPU to a minimum.

In this mode, J-Link temporarily halts the CPU (interrupts the execution of the target application) to access the memory and continues operation automatically after the memory access is done. The actual impact (halted time) on the real time behavior depends on the setup (target interface speed used, target interface used, length of JTAG chain, actual core that is used, ...).

Cores with stop mode support

  • Cortex-A based devices
  • Cortex-R based devices
  • RISC-V based devices

J-Links with stop mode support

Legacy stop mode

In this mode, J-Link temporarily halts the CPU (interrupts the execution of the target application) to access the memory and continues operation automatically after the memory access is done. The actual impact (halted time) on the real time behavior depends on the setup (target interface speed used, target interface used, length of JTAG chain, actual core that is used, ...).

Note: The single operations (halt + acc + go) are triggered from the PC side. This adds significant CPU halt times because there is USB latency between the single operations. The CPU is usually halted for >= 20ms.

Cores with legacy stop mode support

  • All

J-Links with legacy stop mode support

  • All