NXP MCXN10

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The NXP MCXN10 are dual core Arm Cortex-M33 microprocessors.

Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support
Main flash (NS) 0x00000000 Up to 2 MB YES.png
Main flash (S) 0x10000000 Up to 2 MB YES.png

QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for MCXN547 & MCXN947. The default loader is marked in bold.

Device Base address Maximum size Supported pin configuration
QSPI flash (NS) 0x80000000 256 MB *Default CS@P3.0 SCLK@P3.7 D0@P3.8 D1@P3.9 D2@P3.10 D3@P3.11
QSPI flash (S) 0x90000000 256 MB *Default CS@P3.0 SCLK@P3.7 D0@P3.8 D1@P3.9 D2@P3.10 D3@P3.11

ECC RAM

  • Device has ECC RAM with various settings.


Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core CPU0(CM33)

Init/Setup

  • 64KB RAMC @ 0x20010000 is used, if it set to ECC_ENABLE, it is initialized.
  • Enables debugging

Reset

  • Device specific reset is performed.

Attach

  • Attach is supported if RAMC is not set to ECC_ENABLE.

Secondary core CPU1(CM33)

Init/Setup

  • If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
  • If the secondary core is not enabled yet, it will be enabled / release from reset.

Reset

  • No reset is performed, but will halt the CPU.

Attach

  • Attach is supported

Device Specific Handling

Reset

The J-Link performs a device specific reset sequence. The reset is executed for the main core, only. Reset of the main core, resets / disables the secondary core if used in parallel.

Evaluation Boards

Example Application

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