NXP i.MXRT500

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This article covers the NXP i.MXRT500 MCU family devices.

QSPI support

The RT500 does not come with internal flash but with external flash connected to the FlexSPI bus, only. The external FlexSPI controller allows to connect several different flash types like QSPI, HyperFlash and Octaflash. Furthermore, the external flash can be connected to different pin / ports of the FlexSPI controller which makes a auto-detection very difficult thus a out-of-the-box solution which works for all setups is kind of impossible. For that reason, the J-Link software supports the evaluation board setup, only. Other setups may work but without any warranty or guarantee from SEGGER. If you are working with a different setup and looking for support for this setup, please get in touch with SEGGER.

Supported QSPI setup

  • J-Link Software: >= V6.82a
  • Hardware: NXP X-MIMXRT595-EVK (RevC1)
  • Flash: MX25UW51345GXDI00 (octaflash) connected to FlexSPI port A1
Signal Name GPIO name IO function
FLEXSPI0_SCLK PIO1_18 FLEXSPI0_SCLK
RESET_OSPI_MEM PIO1_19 FLEXSPI0_SS0_B
FLEXSPI0_DATA0 PIO1_20 FLEXSPI0_DATA0
FLEXSPI0_DATA1 PIO1_21 FLEXSPI0_DATA1
FLEXSPI0_DATA2 PIO1_22 FLEXSPI0_DATA2
FLEXSPI0_DATA3 PIO1_23 FLEXSPI0_DATA3
FLEXSPI0_DATA4 PIO1_24 FLEXSPI0_DATA4
FLEXSPI0_DATA5 PIO1_25 FLEXSPI0_DATA5
FLEXSPI0_DATA6 PIO1_26 FLEXSPI0_DATA6
FLEXSPI0_DATA7 PIO1_27 FLEXSPI0_DATA7
FLEXSPI0_DQS PIO1_28 FLEXSPI0_DQS
FLEXSPI0_SCLK_N PIO1_29 FLEXSPI0_SS1_N
nRESET_QSPI PIO4_05 PIO4_05

NOTE: The BOOT ROM of the RT500 seems to activate the octa mode under some circumstances. In order to bring the flash into a proper / known state, the J-Link flashloader resets the QSPI flash using the nRESET pin of the flash which is connected to PIO4_05 on the evaluation board. On some preliminary boards, the reset pin was connected to PIO4_24. These boards do not work with the default flashloader.

Example Application

The application toggles the red LED on the MIMXRT595-EVK Rev C1 evaluation board. The application is linked into the external flash. It includes a valid boot header so it also runs stand-alone.

SETUP

i.MXRT595S

This section covers the NXP i.MXRT595S devices.

Streaming trace

The following projects have been tested with the minimum requirements mentioned and a NXP MIMXRT595-EVK Rev C1 evaluation board.

Minimum requirements

In order to use trace on the NXP i.MXRT595S devices, the following minimum requirements have to be met:

  • J-Link software version V6.80a or later
  • Ozone V3.20c or later (if sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace

Tested Hardware

NXP MIMXRT595-EVK Rev C1

Example project

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time

Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time