QSPI Flash Programming Support
More and more CPUs include an so called SPIFI memory controller which allows memory mapped read accesses to any SPI flash, connected to the Quad-SPI interface of the CPU. This allows the J-Link DLL to support flash programming through the Quad-SPI interface of the CPU.
Some CPUs allow to use different port / pin configurations for the connection of the SPI flash. Thus, for each possible pin / port configuration a slightly different flash algorithm is required, even if the same SPI flash and the same CPU is used.
For any supported QSPI Controller SEGGER creates 1-2 example flash loader based on the pin configuration of the evaluation board. Those flash loaders use SEGGERs SPI Flash Interface Library (SPIFI lib) to support a multitude of different SPI flashes. The list of supported SPI flashes is listed on our website. If you choose the same pin layout as used on the evaluation board, the flash algorithms usually can be used out-of-the-box.
Customized Solution Required
If the pin configuration differs from the one listed on the wiki page of the device, you will need a custom flash loader. There are three options for the development of a custom flash loader:
- You may add a custom flash loader yourself with the SEGGER Device Support Kit (DSK).
- You develop a custom flash loader with the help of the existing flash loaders' source code.
- SEGGER develops the custom flash loader for you.
If you are interested in any of those options, please get in touch with SEGGER directly via our support ticket system: https://support.segger.com/.
Multiple flash loader
Any custom pin configuration loader that is developed by SEGGER will be supported through the multiple loader concept. This means that the new pin configuration will be selectable for the device/flash bank.
SPIFI flash loader default behavior
In general, SEGGERs SPIFI flash loaders try to leave the device in the same state as it was before the flash operation. This means that any register, that is used by the flash loader, is initially saved and later restored by the flash loader.
SEGGERs SPIFI flash loader expect the flash to be configured in factory-default state. Any user configuration (e.g. custom dummy-cycle count) that differs from the factory-default is not supported and proper functionality cannot be guaranteed.
Erase is done Block-by-block, which usually means 64 KB. If you require a finer modification of data, we recommend using Read-Modify-Write or a customized flash loader.
Program is done page-by-page. With most flashes this is 256 Bytes.
Quad-Enable (QE) bit
The status register of the SPI flash contains the Quad-Enable (QE) bit which states whether the device is in quad mode or not. SEGGERs SPIFI flash loaders preserve the status of the QE bit before flash programming and restores it to the same state afterwards.
Some devices (e.g. NXP i.MXRT) require the application to have a boot header in which the the QE bit is specified. This then lets the device know how it expects the QE bit in the SPI flashs status register to be set. If the QE bit status within the boot header does not match the QE bit of the flash, the device will not be able to boot from the flash. Since SEGGERs SPIFI flash loaders leave the SPI flash in the same state it was before flash programming, this means that if the QE bit was not set before, it will not be set afterwards.
It is the users responsibility to ensure that the QE bit es set to the correct state.
For i.MXRT the bootloader can set the QE bit if it is accordingly configured within the bootheader. There is an example application for i.MXRT1050 available which does this and can be used as a reference for other iMXRT devices.