SEGGER compiler

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The Segger compiler is based on the LLVM infrastructure and shares exactly the same front-end with Clang (interpretation of C/C++ language), but contains an improved back-end for code generation and optimization for 32-bit ARM CPU's. It uses modified and additional methods for code optimization and is especially useful for small embedded systems, where code size is often an issue. The focus is on Thumb-2 instruction optimization, where the SEGGER compiler usually achieves >= 4% code size reduction and speed improvement compared to the vanilla Clang.

Documentation of the front-end can be found here:

A reference of command line switches of the Segger compiler for use in Embedded Studio (cc1 interface) is listed, when the compiler is invoced with:

 segger-cc -cc1 -help

Language extensions by Segger

The Segger compiler supports the following language extensions:

#pragma location


#pragma location = "<section_name>"

The next declaration of a function or global or static variable following this pragma directive will be placed into the linker section <section_name>.

#pragma data_alignment


#pragma data_alignment = <alignment>

A global or static variable declared immediately after this pragma directive will aligned to a multiple of <alignment> bytes. <alignment> is an integer literal and must be a power of 2.

Additional compiler switches

Switch Description
-mllvm -inline-stack-threshold=<X> All functions with (estimated) stack frame greater than <X> bytes called in the same calling function are either all inlined or none of them are inlined (avoid large stack frame). With <X> set to 0, this check is disabled.

Officially supported CPUs and architectures

While the SEGGER compiler can generate ARM code, only THUMB code generation is tested and verified. 64-bit targets (AARCH64) are not supported.

CPU Architecture
cortex-m0 armv6-m
cortex-m0plus armv6-m
cortex-m1 armv6-m
cortex-m23 armv8-m.base
cortex-m3 armv7-m
cortex-m33 armv8-m.main
cortex-m35p armv8-m.main
cortex-m4 armv7e-m
cortex-m7 armv7e-m
cortex-a5 armv7-a
cortex-a7 armv7-a
cortex-a8 armv7-a
cortex-a9 armv7-a
cortex-a12 armv7-a
cortex-a15 armv7-a
cortex-a17 armv7-a
cortex-r4 armv7-r
cortex-r4f armv7-r
cortex-r5 armv7-r
cortex-r7 armv7-r
cortex-r8 armv7-r

Compiler Invocation

When using stand alone, the Segger compiler accepts the same command line switches as the clang compiler.

The compiler has two different interfaces for command line options: A GCC compatible driver interface and a Clang front-end. The option -cc1 used as the first argument to the compiler indicates that the Clang front-end is to be used, and not the driver. The Clang compiler front-end has several additional Clang specific features which are not exposed through the GCC compatibility driver interface. The clang -cc1 functionality implements the core compiler functionality.

Selecting CPU and architecture

If compiling for a particular CPU with the Segger compiler, the CPU should be specified on the command line and the options -target and -triple should only be used to select the instruction set (arm/thumb) and the endianness.

Mode Options for driver interface Options for Clang compiler interface -cc1
Generate ARM instructions in little endian mode -target arm-none-eabi -mcpu=<cpu> -triple arm-none-eabi -target-cpu <cpu>
Generate THUMB instructions in little endian mode -target thumb-none-eabi -mcpu=<cpu> -triple thumb-none-eabi -target-cpu <cpu>
Generate ARM instructions in big endian mode -target armeb-none-eabi -mcpu=<cpu> -triple armeb-none-eabi -target-cpu <cpu>
Generate THUMB instructions in big endian mode -target thumbeb-none-eabi -mcpu=<cpu> -triple thumbeb-none-eabi -target-cpu <cpu>

Valid CPUs are:

arm1020e arm1020t arm1022e arm10e arm10tdmi arm1136j-s arm1136jf-s arm1156t2-s arm1156t2f-s arm1176j-s arm1176jz-s arm1176jzf-s arm710t arm720t arm7tdmi arm7tdmi-s arm8 arm810 arm9 arm920 arm920t arm922t arm926ej-s arm940t arm946e-s arm966e-s arm968e-s arm9e arm9tdmi cortex-a12 cortex-a15 cortex-a17 cortex-a32 cortex-a35 cortex-a5 cortex-a53 cortex-a55 cortex-a57 cortex-a7 cortex-a72 cortex-a73 cortex-a75 cortex-a76 cortex-a76ae cortex-a8 cortex-a9 cortex-m0 cortex-m0plus cortex-m1 cortex-m23 cortex-m3 cortex-m33 cortex-m35p cortex-m4 cortex-m7 cortex-r4 cortex-r4f cortex-r5 cortex-r52 cortex-r7 cortex-r8 strongarm strongarm110 strongarm1100 strongarm1110

If compiling code that should run on multiple CPUs, the architecture can be specified using the -target or -triple option:

 -target <mode><endian><version>-none-eabi  (Option for driver interface)
 -triple <mode><endian><version>-none-eabi  (Option for Clang compiler interface -cc1)


  • <mode> is the instruction mode: "arm" or "thumb".
  • <endian> is empty for little endian or "eb" for big endian.
  • <version> is the ARM architecture version. Valid versions are:

v4 v4t v5t v5te v5tej v6 v6k v6t2 v6kz v6m v7a v7ve v7r v7m v7em v7s v7k v8a v8.1a v8.2a v8.3a v8.4a v8.5a v8.6a v8r v8m.base v8m.main v8.1m.main


 -triple thumbv7m-none-eabi
 -triple armebv4t-none-eabi

Optimization levels

Switch Description
-O0 No optimization (debug build)
-O1 Optimization level 1
-O2 Optimization level 2 for speed
-Os Optimization level 2 (balanced)
-Oz Optimization level 2 for size
-O3 Optimization level 3 for speed

Recommended options

If using the compiler via the command line (especially when building libraries) some compiler options should be considered to be used to generate code compatible with Embedded Studio.

Option for Clang compiler interface -cc1 Option for driver interface Description
-fgnuc-version=4.2.1 -fgnuc-version=4.2.1 Define macros __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__ and __GNUG__
Required for example for CMSIS files.
-ffunction-sections -fdata-sections -ffunction-sections -fdata-sections Place each function and data in its own section.
Strongly recommended.
-mrelocation-model static N.A. Don't generate position independent code.
Strongly recommended.
-fshort-enums -fshort-enums Allocate to an enum type only as many bytes as it needs for the declared range of possible values.
Strongly recommended.
-target-feature +strict-align -mno-unaligned-access Force all memory accesses to be aligned.
Recommended for libraries.
N.A. Don't run the LLVM IR verifier pass.
Disable freeing of memory on exit.
Optional. May speed up compilation.
-fmath-errno -fmath-errno Require math functions to indicate errors by setting errno.
Set by Embedded Studio. Why ?
-fno-common -fno-common Compile common globals like normal definitions.
Set by Embedded Studio. Why ?
-exception-model=dwarf -fdwarf-exceptions Generate .debug_frame sections in ELF file to enable unwinding call stack while debugging.
-mllvm -generate-arange-section -mllvm -generate-arange-section Set by Embedded Studio. Why ?

Target features

If given a target CPU, several options (called target features) are implicit set depending on the selected CPU. These are listed in the table below. If one or more of these features should not be used, they must be explicitly disabled using -target-feature -<option>.

For better handling of the target features, the Segger compiler has two additional command line switches:

If -target-feature +list is specified, the compiler will print a list of target features actually effective to stderr.

With -target-feature -implicit-fp all implicit target features that are related to the floating point capabilities of the target will be disabled. This option should always be used together with the option -target-feature +soft-float.

These options are available in the Clang compiler front-end (-cc1) only.

Implicit target features

CPU Feature
cortex-m0 +armv6-m +thumb-mode
cortex-m0plus +armv6-m +thumb-mode
cortex-m1 +armv6-m +thumb-mode
cortex-m23 +armv8-m.base +hwdiv +thumb-mode
cortex-m3 +armv7-m +hwdiv +thumb-mode
cortex-m33 +armv8-m.main +dsp +fp-armv8d16sp +fp16 +hwdiv +thumb-mode +vfp2sp +vfp3d16sp +vfp4d16sp
cortex-m35p +armv8-m.main +dsp +fp-armv8d16sp +fp16 +hwdiv +thumb-mode +vfp2sp +vfp3d16sp +vfp4d16sp
cortex-m4 +armv7e-m +dsp +fp16 +hwdiv +thumb-mode +vfp2sp +vfp3d16sp +vfp4d16sp
cortex-m55 +armv8.1-m.main +dsp +fp-armv8d16 +fp-armv8d16sp +fp16 +fp64 +fullfp16 +hwdiv +lob +mve +mve.fp +ras +thumb-mode +vfp2 +vfp2sp +vfp3d16 +vfp3d16sp +vfp4d16 +vfp4d16sp
cortex-m7 +armv7e-m +dsp +fp-armv8d16sp +fp16 +hwdiv +thumb-mode +vfp2sp +vfp3d16sp +vfp4d16sp
cortex-a12 +armv7-a +d32 +dsp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a15 +armv7-a +d32 +dsp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a17 +armv7-a +d32 +dsp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a32 +armv8-a +crc +crypto +d32 +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a35 +armv8-a +crc +crypto +d32 +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a5 +armv7-a +d32 +dsp +fp16 +fp64 +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a53 +armv8-a +crc +crypto +d32 +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a55 +armv8.2-a +crc +crypto +d32 +dotprod +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +fullfp16 +hwdiv +hwdiv-arm +neon +ras +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a57 +armv8-a +crc +crypto +d32 +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a7 +armv7-a +d32 +dsp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a72 +armv8-a +crc +crypto +d32 +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a73 +armv8-a +crc +crypto +d32 +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a75 +armv8.2-a +crc +crypto +d32 +dotprod +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +fullfp16 +hwdiv +hwdiv-arm +neon +ras +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a76 +armv8.2-a +crc +crypto +d32 +dotprod +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +fullfp16 +hwdiv +hwdiv-arm +neon +ras +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a76ae +armv8.2-a +crc +crypto +d32 +dotprod +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +fullfp16 +hwdiv +hwdiv-arm +neon +ras +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-a8 +armv7-a +d32 +dsp +fp64 +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp -thumb-mode
cortex-a9 +armv7-a +d32 +dsp +fp16 +fp64 +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp -thumb-mode
cortex-r4 +armv7-r +dsp +hwdiv -thumb-mode
cortex-r4f +armv7-r +dsp +fp64 +hwdiv +vfp2 +vfp2sp +vfp3d16 +vfp3d16sp -thumb-mode
cortex-r5 +armv7-r +dsp +fp64 +hwdiv +hwdiv-arm +vfp2 +vfp2sp +vfp3d16 +vfp3d16sp -thumb-mode
cortex-r52 +armv8-r +crc +d32 +dsp +fp-armv8 +fp-armv8d16 +fp-armv8d16sp +fp-armv8sp +fp16 +fp64 +hwdiv +hwdiv-arm +neon +vfp2 +vfp2sp +vfp3 +vfp3d16 +vfp3d16sp +vfp3sp +vfp4 +vfp4d16 +vfp4d16sp +vfp4sp -thumb-mode
cortex-r7 +armv7-r +dsp +fp16 +fp64 +hwdiv +hwdiv-arm +vfp2 +vfp2sp +vfp3d16 +vfp3d16sp -thumb-mode
cortex-r8 +armv7-r +dsp +fp16 +fp64 +hwdiv +hwdiv-arm +vfp2 +vfp2sp +vfp3d16 +vfp3d16sp -thumb-mode