ST SR6P7G7x
Contents
The ST SR6P7G7x are Stellar P series microcontroler, which inlcude 10 Cortex-R52+ and 3 Cortex-M4.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| RWW Partition 0 | 0x28000000 | 1792 KB | 
|
| RWW Partition 1 | 0x281C0000 | 2048 KB |
|
| RWW Partition 2 | 0x28400000 | 1792 KB |
|
| RWW Partition 3 | 0x285C0000 | 2048 KB |
|
| RWW Partition 4 | 0x28800000 | 2048 KB |
|
| RWW Partition 5 | 0x28C00000 | 2048 KB |
|
| RWW Partition 6 | 0x29000000 | 2048 KB |
|
| RWW Partition 7 | 0x29400000 | 2048 KB |
|
| EEPROM / RWW 8 | 0x29E00000 | 512 KB |
|
| UTEST / RWW 1 | 0x29F80000 | 32 KB |
|
| Boot Code Sector / RWW 1 | 0x29FB8000 | 16 KB |
|
| HSM Code / RWW 9/10 | 0x00000000 | 512 KB | 
|
| HSM Data / RWW 11 | 0x003A0000 | 128 KB |
|
| HSM UT / RWW 11 | 0x0037C000 | 16 KB |
|
Flash programming
Flash programming of all above listed flash regions is done through Cluster0 Core0 (Cortex-R52).
The flash controller has no explicit erase function.
When reprogramming flash an explicit erase before programming is not necessary. Already programmed flash can be directly reprogrammed.
ECC Flash
Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.
ECC RAM
Device has ECC RAM, init before first use is necessary. Please refer to the reference Manual. ECC RAM initialization is done for Cluster 0 Core 0, see below.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR6P7G7 family comes with 10 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-R52 Cluster 0 Core 0
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
Reset
- ARMv8-R Reset is performed like described here.
- Initializes 256KB ECC RAM starting at 0x60000000
- WDT is enabled by default. If it is enabled, it will be disabled.
Attach
- Attach is supported, user has to take care about ECC RAM initialization.
Cortex-R52 Cluster 0 Core 1
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 1
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cortex-R52 Cluster 2 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
DSPH Core
Init/Setup
- none
Reset
- Cortex-M Typ 0 normal reset is performed like described here.
Attach
- Attach is supported
DME Core
Init/Setup
- none
Reset
- Cortex-M Typ 0 normal reset is performed like described here.
Attach
- Attach is supported
Device Specific Handling
Reset
- Depending on connected core, different resets are performed, see above.
