ST STM32U5

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The ST STM32U5 series are 32-bit ultra low power microcontrollers based on the ARM Cortex-M33 processor.


Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support
Non-Secure Internal Flash 0x08000000 Up to 4MB YES.png
Secure Internal Flash 0x0C000000 Up to 4MB YES.png
User Option 0x40022040 48B NO.png


QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.


The ST STM32U5 device series comes with OCTASPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Octa-SPI interface of the MCU. J-Link supports for the STM32U5:

  • One single or quad SPI device connected to D0 to D3
  • Two single or quad SPI devices connected to D0 to D7 (dual mode)

Octo SPI is not supported yet.

Some STM32U5 sub-family devices additionally come with HSPI controller which also allow memory mapped read access to any (Q)SPI flash, connected to the Hexadeca-SPI interface of the MCU. J-Link support for the STM32U5Gxxx:

  • One single or quad SPI device connected to HSPI1 GPIOs on Port H.

Other SPI modes are not supported yet.

J-Link supports multiple pin configurations for STM32U5. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.

Device Base address Maximum size Supported pin configuration
  • STM32U575
  • STM32U585
  • STM32U5A9
0x90000000 up to 64 MB
  • CLK@PF4_nCS@PI5_D0@PF0_D1@PF1_D2@PF2_D3@PF3
  • CLK@PF10_nCS@PA2_D0@PF8_D1@PF9_D2@PF7_D3@PF6
  • CLK@PH6_nCS@PI5_D0@PI3_D1@PI2_D2@PI1_D3@PH8
  • STM32U5G9
0xA0000000 up to 64 MB
  • CLK@PI3_nCS@PH9_D0@PH10_D1@PH11_D2@PH12_D3@PH13_D4@NA_D5@NA_D6@NA_D7@NA


For pin configuration, different from the one used in the example flash algorithm, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

Device family

The STM32U5 device family consists of several subfamilies:

Subfamily Flash size Remarks
STM32U535 128KB to 512KB QSPI not supported yet
STM32U545 512KB QSPI not supported yet
STM32U575 1MB to 2MB
STM32U585 2MB
STM32U599 2MB to 4 MB
STM32UA9 4 MB

Watchdog Handling

  • The device has a watchdog IWDG.
  • The watchdog is fed during flash programming and stopped during halt.

Reset

For the STM32U5 devices, the Cortex-M default reset strategy is used.

Debug specific

Please refer to the generic STM32 article.

Option byte programming

Direct option byte programming is not (yet) implemented for the ST STM32U5. However, the same method used to lock/unlock the devices can be used as described in Securing/unsecuring the device can be used to adjust any option bytes.

Securing/unsecuring the device

Please refer to the generic STM32 article.

TrustZone

The TrustZone feature may be used for the STM32U5 devices, however, there are a couple of limitations that have to be kept in mind:

  • Flash programming with TrustZone enabled (TZEN = 1) is generally supported when RDP level is 0 or 0.5.
  • For programming RDP level 0.5 a RAMless flashloader has to be used due to a technical limitation.
    Please note that a significantly lower programming speed has to be expected when using the RAMless flashloader.
  • The J-Link software can not determine whether to use the RAMCode or RAMless flashloader, so it is user responsibility to select the correct flashloader beforehand, by adding "_RAMLess" to the device name, e.g. use "STM32U599NJ_RAMLess" instead of "STM32U599NJ".

Clearing TZEN via J-Link

To disable TrustZone via debug probe, an RDP regression has to be performed (RDP Level 1 => 0). However if TZEN == 1 and RDP Level == 1, a debug connection can only be established while the device is executing non-secure code. To make sure that the device is executing non-secure code, it can be forced to boot in ST bootloader mode.
The following J-Link Script file can be used to automatically disable TrustZone on connect:

Note:
Regressing RDP from Level 1 to 0 will trigger a mass erase of the device.

Evaluation Boards

Example Application

Example Application

The following example project was created with the SEGGER Embedded Studio project wizard and should run out-of-the-box on any ST STM32U5xxxx device. It is a simple for loop incrementing the integer i. The application is linked into the internal flash.
SETUP

Tracing on ST STM32U5

Tracing on ST STM32U575

The following project has been tested with the minimum requirements mentioned and a ST STM32U575I-EVAL evaluation board.

Minimum requirements

In order to use trace on the ST STM32U575 MCU devices, the following minimum requirements have to be met:

  • J-Link software version V7.66d or later
  • Ozone V3.26b or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Streaming trace

Example Project: ST_STM32U575I_EV_TraceSample.zip

Note: The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing

Tested Hardware

ST STM32U575I-EVAL

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time
Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time