SiFive E21

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The SiFive E21 is a 32-bit (RV32) core of the SiFive E2 series cores, designed by SiFive.

Minimum required J-Link software version

The E21 and E21ARTY device selection are supported since V7.22 of the J-Link software.

E21ARTY device selection

The E21ARTY is a special device that can be selected for J-Link. It selects the standard SiFive E21 that is implemented for the sample bitstream as part of the SiFive E21 Standard Core Dev Kit. Device specifics include:

  • Memory map
  • Flash banks

As the E21 is a customizable core, the E21ARTY selection may not be appropriate for customized cores but for the standard one running on the ARTY-100T FPGA evaluation board only.

RTT support

As the core does not support System Bus Access (SBA), RTT is not supported for this core.

HSS access

As the core does not support System Bus Access (SBA), HSS is not supported for this core.

Tracing on SiFive E21 cores

This section describes how to get started with trace on the SiFive E21 core MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).


  • The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
  • The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing and Ozone.
  • In order to rebuild the sample project, SEGGER Embedded Studio can be used.

Minimum requirements

In order to use trace on the SiFive E21 core MCUs, the following minimum requirements have to be met:

  • J-Link software version V7.84e or later
  • Ozone V3.26h or later (if the sample project from below shall be used)
  • J-Trace PRO for RISC-V HW version V3.0 or later for streaming trace
  • J-Link Plus V11 or later for buffer trace
  • The bitstream used in the FPGA board must support SiFive Nexus BTM tracing

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Streaming trace

The project below has been tested with the minimum requirements mentioned above and a Digilent AVNET ARTY A7 100T board. The board is loaded with an FPGA bitstream for the SiFive E21 core. The bitstream must support SiFive Nexus BTM with trace pins as a trace sink option.

FPGA bitstreams can be requested at the SiFive website.

For connection of the board to the J-Trace Pro RISC-V the SiFive ARTY Trace Adapter may be used.

Example project:

Trace buffer

For buffer tracing the same project above can be used. Simply change the trace settings in Ozone to trace buffer via Tools->Trace Settings...->Trace Source-> Trace Buffer

Tested Hardware

Digilent AVNET ARTY A7 100T