Tracing on ST STM32F407 (SEGGER Cortex-M Trace Reference Board)
This article describes how to get started with trace on the ST STM32F407 MCU. This article assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001). The ST STM32F407 MCU implements tracing via pins, so a J-Trace can be used for tracing.
In order to use trace on the ST STM32F407MCU devices, the following minimum requirements have to be met:
- J-Link software version V6.44 or later
- Ozone V2.60p or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later
The following sample project is designed to be used with J-Trace PRO and Ozone to demonstrate streaming trace. The project has been tested with the minimum requirements mentioned above and a SEGGER Cortex-M Trace Reference Board which is part of each J-Trace PRO purchase. The sample project comes with a pre-configured project file for Ozone that runs out-of-the box. In order to rebuild the sample project, SEGGER Embedded Studio can be used.
Tutorial Project: J-Trace Streaming Trace tutorial project
The following is a bare bone example with tracing at maximum trace clock speed the Trace Reference Board supports.
Max. Trace clock speed + JLinkScript sample: ST_STM32F407_84MHz_TraceExample.zip
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.