Using RTT on RZ A1H
This page explains how to use SEGGER Real-Time-Terminal (RTT) on the Renesas RZ/A1H family devices. As the setup on the target project side is slightly different from IDE to IDE, in the following some sample setups for different IDEs are explained.
SEGGER Embedded Studio
There is a sample project for Embedded Studio available that demonstrates how to configure the project + target application for using RTT with Renesas RZ/A1H on a RSK-RZA1H starter kit. The sample project can be downloaded here:
The sample project is based on a generic SEGGER embOS trial start project for the Renesas RSK-RZA1H starter kit with some modifications to make it usable with RTT.
The following are the minimum requirements to use RTT on the Renesas RZ:
- Embedded Studio V2.14 or later
- A current J-Link model
- J-Link software V5.11d (beta), V5.20 (release) or later
Specifics modifications in sample project
In the following, the specific modifications that have been performed on the example project, are explained.
The RTT control block as well as the RTT buffers have to be located in a uncached memory region for which physical address is identical to the virtual address. The MMU configuration functions of embOS 1 MB MMU regions/memory blocks. The MMU is configured in __low_level_init() of Setup\RTOSInit_R7S72100.c:
// Init MMU and caches. This defines the virtual memory map, which is used during execution. // Memory mapping should be complete, meaning 4096 entries. // Code below fills in ascending VAddr order // OS_ARM_MMU_InitTT(_TranslationTable); // Mode VAddr PAddr Size[MB] OS_ARM_MMU_AddTTEntries(_TranslationTable, OS_ARM_CACHEMODE_C_NB, 0x000, 0x000, 0x040); // CS0 space, 64MB NOR Flash (16bit BUS on Eval-Board) [...] OS_ARM_MMU_AddTTEntries(_TranslationTable, OS_ARM_CACHEMODE_NC_NB, 0x600, 0x600, 0x001); // 1MB internal RAM mirror space => Reserved for RTT OS_ARM_MMU_AddTTEntries(_TranslationTable, OS_ARM_CACHEMODE_C_B, 0x601, 0x601, 0x009); // 9MB internal RAM mirror space, used as RAM for application
Memory region assignment
After reserving a specific memory region for the RTT variables, the linker needs to be told to place the variables in this memory region.
<Root name="ARM" > <MemorySegment start="0x60020000" size="0x0E0000" access="Read/Write" name="RTT_AREA" /> <MemorySegment start="$(SRAM_START:0x60100000)" size="$(SRAM_SIZE:0x900000)" access="Read/Write" name="SRAM" /> </Root>
<Root name="SRAM Section Placement"> [...] <MemorySegment name="$(ISRAM_NAME:Internal SRAM);SRAM;SDRAM;DRAM"> <ProgramSection load="Yes" name=".vectors" /> <ProgramSection alignment="4" load="Yes" name=".fast" /> </MemorySegment> <MemorySegment name="RTT_AREA"> <ProgramSection alignment="4" load="No" name=".bss._SEGGER_RTT" /> <ProgramSection alignment="4" load="No" name=".bss._acUpBuffer" /> <ProgramSection alignment="4" load="No" name=".bss._acDownBuffer" /> </MemorySegment> </Root>
RTT variable initialization
As the RTT variables are no longer part of the regular .bss section, they are no longer be initialized via the standard startup code delivered with the embOS trial project. Some lines of code need to be added to crt0.s to make sure the static RTT variables (control block and buffers) are zero-initialized:
[...] ldr r0, =__tbss_start__ ldr r1, =__tbss_end__ mov r2, #0 bl memory_set /**/ /*Initialize RTT area*/ /**/ ldr r0, =__RTT_AREA_segment_start__ ldr r1, =__RTT_AREA_segment_used_end__ mov r2, #0 bl memory_set [...]
RTT control block location specification
In order to make sure that the J-Link DLL only scans the memory area reserved for RTT, an explicit RTT search range is passed to the J-Link DLL on debug session start, through Project -> Properties -> Debugger -> J-Link Options -> Execute J-Link Commands on Connect:
SetRTTSearchRanges 0x60020000 0xE0000