Xilinx Zynq-7000
Contents
The Xilinx Zynq-7000 are Cortex-A9 based microcontrollers
Flash Banks
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports QSPI programming for Zynq-7000 for the flash bank located at 0xFC000000. There are multiple loaders available. The default loader assumes that an external osciallator running at 33 MHz is used and uses this as a base clock for the PLL to run the flash programming at 50 MHz. If you are using an oscillator that is running faster than 33 MHz, we recommend using the NoPLLInit loader. Otherwise proper execution of the flash operation is not guaranteed.
| Device | Base address | Maximum size | Available loaders |
|---|---|---|---|
| XA7Z010 XA7Z020 XC7Z007S XC7Z012S XC7Z014S XC7Z010 XC7Z015 XC7Z020 XC7Z030 XC7Z035 XC7Z045 XC7Z100 XQ7Z020 |
0xFC000000 | 16 MB |
|
Device Specifc Handling
Reset
- The devices uses normal Cortex-A reset, no special handling necessary, like described here.
Evaluation Boards
- Xilinx ZedBoard evaluation board: https://wiki.segger.com/Zedboard_Evalboard
- Xilinx MicroZed evaluation board: https://wiki.segger.com/MicroZed_Evalboard
Tracing on Zynq series
Tracing on Xilinx Zynq
Minimum requirements
In order to use trace on the Xilinx Zynq SoC, the following minimum requirements have to be met:
- J-Link software version V7.92n or later
- Ozone V3.30c or later (if streaming trace and / or the sample project from below shall be used)
- SEGGER Embedded Studio V7.32
- J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace
- J-Link Plus V12 or later for ETB trace
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Streaming trace
The project has been tested with the minimum requirements mentioned above and a trace capable board. Trace board design recommendations can be found here: Trace board design recommendations
Example project: Xilinx_Zynq_XC7007_TracePins.zip
Note: The example is shipped with a compiled .JLinkScriptfile which will initialize the following MIO pins as trace pins: TCLK = PS_MIO24_501, TD0 = PS_MIO26_501, TD1 = PS_MIO27_501, TD2 = PS_MIO22_501, TD3 = PS_MIO23_501. Should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/. If you are routing the trace pins via the FPGA no additional script file is needed, you only need to have the J-Link software version installed listed under "Minimum requirements".
To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing
Pin tracing via the FPGA
The Xilinx Zynq family supports routing the trace pins via the FPGA circuit for more flexibility. Please note that in that case you will need to make sure that the FPGA image has been programmed and loaded before starting to trace your application in the Cortex-A9 main core, otherwise trace data might be missing.
Trace buffer (ETB)
Example Project: Xilinx_Zynq_XC7007_TraceBuffer.zip
