Xilinx Zynq UltraScalePlus

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This article describes device specifics of the Xilinx Zynq UltraScale+ series devices.


The Zynq UltraScale+ series consists of the following families:

  • Zynq UltraScale+ CG (2x Cortex-A53, 2x Cortex-R5)
  • Zynq UltraScale+ DR (4x Cortex-A53, 2x Cortex-R5)
  • Zynq UltraScale+ EG (4x Cortex-A53, 2x Cortex-R5)
  • Zynq UltraScale+ EV (4x Cortex-A53, 2x Cortex-R5)

Debugging the Cortex-R5

In order to connect to and debug one of the available Cortex-R5 on the UltraScale+ series, an UltraScale+ device with XCZU..._R5_0 must be selected. For a list of supported device names, please refer to the list of supported devices on the SEGGER website.

Software requirements

J-Link software V6.45c or later is required. Older versions will not work.


When connecting to the Cortex-R5, J-Link will by default reset the Cortex-R5 core it connects to and halt it via vector catch. In order to alter this behavior, please get in touch with SEGGER support to get the sources of the connect sequence for this device.


When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-R5 core it is connected to. No peripherals or other cores will be reset.

Example project

The following example project is for SEGGER Embedded Studio V4.12 and later. It loads a simple Cnt++ loop application into the OCM RAM of the Zynq UltraScale+.

File:Xilinx XCZU3EG R5 0 CntLoop ES.zip

Debugging the Cortex-A53