i.MX7ULP

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The NXP i.MX7ULP are multicore MCUs consisting of a Cortex-M4 and Cortex-A7.

Flash Banks

QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.

Device Base address Maximum size
MCIMX7U3_M4
MCIMX7U5_M4
0x04000000 128 MB
MCIMX7U3_A7
MCIMX7U5_A7
0xC0000000 128 MB

The following QSPI interface is used on the iMX7ULP-EVK-SOM board to interface the (Q)SPI flash.

Alternate function Port / Pin
QSPIA_SS0_B (AF8) PTB8
QSPIA_SCLK (AF8) PTB15
QSPIA_DATA3 (AF8) PTB16
QSPIA_DATA2 (AF8) PTB17
QSPIA_DATA1 (AF8) PTB18
QSPIA_DATA0 (AF8) PTB19

Watchdog Handling

  • The watchdogs WDOG0, WDOG1 and WDOG2 are fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Cortex-M4

Init/Setup

  • Enables debugging
  • Disables MPU

Reset

No reset is performed.

Cortex-A7

Init/Setup

Core is enabled by setting A7_CORE1_ENABLE bit in SRC_A7RCR1 register.

Reset

No reset is performed.

Evaluation Boards

Example Application