i.MX8

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The NXP i.MX8 is a embedded multicore processor consisting of one Cortex-M4 and four Cortex-A53 and two Cortex-A72.

Debugging

J-Link supports debugging for the Cortex-M4. During connect the M4 is set to execute an endless loop at 0x1FFE0000 (TCML RAM) and afterwards halted.

Reset

J-Link currently does not support device reset.

Implementation

The support of these devices has been implemented in part by SEGGER and in part by NXP.

Following table shows an overview of all currently supported i.MX8 devices:

Device Implementation
MIMX8DL1_M4 NXP
MIMX8DX1_M4 NXP
MIMX8DX2_M4 NXP
MIMX8DX3_M4 NXP
MIMX8DX4_M4 NXP
MIMX8DX5_M4 NXP
MIMX8DX6_M4 NXP
MIMX8MD6_M4 SEGGER
MIMX8MD7_M4 SEGGER
MIMX8ML3_M7 NXP
MIMX8ML4_M7 NXP
MIMX8ML6_M7 NXP
MIMX8ML8_M7 NXP
MIMX8MM1_M4 SEGGER
MIMX8MM2_M4 SEGGER
MIMX8MM3_M4 SEGGER
MIMX8MM4_M4 SEGGER
MIMX8MM5_M4 SEGGER
MIMX8MM6_M4 SEGGER
MIMX8MN1_M7 NXP
MIMX8MN2_M7 NXP
MIMX8MN3_M7 NXP
MIMX8MN4_M7 NXP
MIMX8MN5_M7 NXP
MIMX8MN6_M7 NXP
MIMX8MQ5_M4 SEGGER
MIMX8MQ6_M4 SEGGER
MIMX8MQ7_M4 SEGGER
MIMX8QM5_M4_0 NXP
MIMX8QM5_M4_1 NXP
MIMX8QM6_M4_0 NXP
MIMX8QM6_M4_1 NXP
MIMX8QX1_M4 NXP
MIMX8QX2_M4 NXP
MIMX8QX3_M4 NXP
MIMX8QX4_M4 NXP
MIMX8QX5_M4 NXP
MIMX8QX6_M4 NXP
MIMX8SL1_M4 NXP
MIMX8UX5_M4 NXP
MIMX8UX6_M4 NXP