i.MXRT1050

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This article covers the NXP i.MXRT1050 family devices. As for all i.MXRT10xx devices, JTAG is not active per default. Instead SWD can be used. To activate JTAG on this target device eFuses must be set. For more information see the corresponding target reference manual.

Flash Programming

NXP's iMXRT105x family features a Cortex-M7 core without internal flash but with support for QSPI and HyperFlash through a so called FLEXSPI controller. NXP's official evaluation board, the MIMXRT1050 EVK is shipped with a 512Mbit Hyper Flash device by default. Alternatively, a QSPI flash can be mounted but several board modifications (removing the hyper flash, adding resistors, etc...) are required. As both flashes are accessed through the same memory mapped address space, either the HyperFlash or the QSPI flash RAMCode needs to be used for memory accesses to this area. Please find below further information how to enable the desired flash algorithm (RAMCode). Official flash programming support has been added in J-Link software version V6.31d.

Minimum requirements

  • Min. J-Link software version V6.31d (beta) or V6.32 (release) is required. Later versions will also work. Earlier versions do not support flash programming on this device.

Available flash loaders

J-Link comes with multiple selectable FLEXSPI flashloaders for i.MXRT1050 devices. There are several options to select a different loader than the default one.

Loader name Pin configuration Notes
HyperFlash FLEXSPIB_DATA03 = GPIO_SD_B1_00
FLEXSPIB_DATA02 = GPIO_SD_B1_01
FLEXSPIB_DATA01 = GPIO_SD_B1_02
FLEXSPIB_DATA00 = GPIO_SD_B1_03
FLEXSPIB_SCLK = GPIO_SD_B1_04
FLEXSPIA_DQS = GPIO_SD_B1_05
FLEXSPIA_SS0_B = GPIO_SD_B1_06
FLEXSPIA_SCLK = GPIO_SD_B1_07
FLEXSPIA_DATA00 = GPIO_SD_B1_08
FLEXSPIA_DATA01 = GPIO_SD_B1_09
FLEXSPIA_DATA02 = GPIO_SD_B1_10
FLEXSPIA_DATA03 = GPIO_SD_B1_11
Default loader
QSPI FLEXSPIB_DATA03 = GPIO_SD_B1_00
FLEXSPIB_DATA02 = GPIO_SD_B1_01
FLEXSPIB_DATA01 = GPIO_SD_B1_02
FLEXSPIB_DATA00 = GPIO_SD_B1_03
FLEXSPIB_SCLK = GPIO_SD_B1_04
FLEXSPIA_DQS = GPIO_SD_B1_05
FLEXSPIA_SS0_B = GPIO_SD_B1_06
FLEXSPIA_SCLK = GPIO_SD_B1_07
FLEXSPIA_DATA00 = GPIO_SD_B1_08
FLEXSPIA_DATA01 = GPIO_SD_B1_09
FLEXSPIA_DATA02 = GPIO_SD_B1_10
FLEXSPIA_DATA03 = GPIO_SD_B1_11
-
Note:
Please note that several hardware modifications needs to be done on the evaluation board to enable QSPI programming / booting from QSPI. For further information regarding this, please refer to NXPs board user manual.

Examples

The example projects below can be used to evaluate Hyper Flash and QSPI Flash programming support with J-Link using a simple blinky project. The projects include the boot header, required for booting the application without an external debugger attached to it. Please find below an overview of the setup:

  • SEGGER Embedded Studio for ARM 3.35
  • NXP MIMXRT1050-EVK (Hyper Flash configuration for Hyper Flash example and QSPI Flash configuration for QSPI Flash example)
  • J-Link software version V7.70d or higher

Hyper Flash

  1. Make sure that SEGGER Embedded Studio for ARM 3.35 is installed
  2. Install at least J-Link software version V7.70d and update the J-Link DLL used by Embedded Studio at the end of the setup process (using the J-Link DLL Updater)
  3. Download the project File:NXP MIMXRT1050-EVK HyperFlash EmbeddedStudio.zip
  4. Open the project in Embedded Studio
  5. Done!

QSPI Flash

  1. Make sure that SEGGER Embedded Studio for ARM 3.35 or later is installed
  2. Install at least J-Link software version V7.70d and update the J-Link DLL used by Embedded Studio at the end of the setup process (using the J-Link DLL Updater)
  3. Download the project File:NXP MIMXRT1050-EVK QSPI EmbeddedStudio.zip
  4. Open the project in Embedded Studio
  5. Done!

NOTE: Please note that several hardware modifications needs to be done on the evaluation board to enable QSPI programming / booting from QSPI. For further information regarding this, please refer to NXPs board user manual.
NOTE: The QSPI example application contains a FlexSPI boot header, which makes sure that the QE bit in the status register is set.