ATSAME70

SWO

On the ATSAME70 series devices from Microchip SWO is supported. However, a few device specifics apply which are described in the following section.

Clock source

For most devices, the SWO clock is derived from the current MCU clock. This is also the case for the ATSAME70 series devices. However on these devices, the SWO clock source is disabled after reset and multiple sources and dividers can be selected.

Note: J-Link handles the current setting of this register automatically when calculating the SWO speed to be used. J-Link software version V6.32a or later is required.

The following settings are used:

• SWO clock source is MCK
• SWO clock divider is set to 14+1 assuming MCK is 150 MHz after reset and is not changed by application.

Note: The settings are applied by a compiled .JLinkScriptfile located in the J-Link software installation folder under /Devices, should you need the original source it can be requested at support@segger.com

Note: When selecting the CPU frequency in IDEs for J-Link SWO usage, select 300 MHz for the ATSAME70 series devices.