Difference between revisions of "AlifSemi CxEx"

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The '''Alif Semiconductor CxEx ''' MCUs create a scalable and compatible continuum of highly integrated embedded processor devices for use in low-end to high-end
__TOC__
 
The families of fusion processors and microcontrollers (MCUs) from Alif Semiconductor create a scalable and compatible continuum of highly integrated embedded processor devices for use in low-end to high-end
 
 
intelligent IoT end-point applications. Architected for power efficiency and long battery life, these devices deliver high computation and ML/AI capability, multi-layered security, computer vision, and highly interactive human-machine interface.
 
intelligent IoT end-point applications. Architected for power efficiency and long battery life, these devices deliver high computation and ML/AI capability, multi-layered security, computer vision, and highly interactive human-machine interface.
   
  +
__TOC__
==Debug Support==
 
The J-Link support for the Crescendo and Ensemble includes both Cortex-M55 cores, and both Cortex-A32 cores.
 
The user can configure the accessiblity of the cores with the Alif Security Toolkit.
 
   
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==Flash Banks==
==On-Chip Memory Regions==
 
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===Flash===
The internal flash is called MRAM:
 
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{| class="seggertable"
 
{| class="wikitable"
 
 
|-
 
|-
! Instance Name !! Size (mega bytes) || Memory region
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! Flash Bank || Base address !! Size || J-Link Support
 
|-
 
|-
| Bank 0 || up to 5.75|| 0x80000000 - 0x805C0000
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| Internal flash || 0x80000000 || Up to 5.75 MB || style="text-align:center;"| {{YES}}
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|-
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| OSPI flash || 0xC0000000 || Up to 32 MB || style="text-align:center;"| {{YES}}
 
|}
 
|}
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{{Note|1=
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* OSPI flash programming is supported for IS25WX256 only
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}}
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==Watchdog Handling==
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*The watchdog is fed during flash programming.
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==Multi-Core Support==
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Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br>
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The [DeviceFamily]family comes with a variety of multi-core options.<br>
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Some devices from this family feature a secondary core which is disabled after reset / by default.<br>
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Some of the are available with enabled ''lockstep'' mode, only. <br>
  +
In below, the debug related multi-core behavior of the J-Link is described for each core:
  +
  +
The J-Link support for the Ensemble devices includes both Cortex-M55 cores, and both Cortex-A32 cores.
  +
The user can configure the accessibility of the cores with the Alif Security Toolkit.
   
 
==Example Application==
 
==Example Application==
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'''SETUP'''
 
'''SETUP'''
 
*J-Link software: V7.61e
 
*J-Link software: V7.61e
*Embedded Studio: V5.68
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*Embedded Studio: V6.13
 
*Hardware: DK-E7-BNDL-A1 Ensemble E7 Beta Development Kit (DevKit) with Baseboard + CPU Board
 
*Hardware: DK-E7-BNDL-A1 Ensemble E7 Beta Development Kit (DevKit) with Baseboard + CPU Board
*Link: [[File:AlifSemi_CxEx_TestProject_ES_V568.zip]]
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*Link: [[File:AlifSemi_CxEx_TestProject_ES_V613.zip]]

Latest revision as of 13:21, 6 March 2024

The Alif Semiconductor CxEx MCUs create a scalable and compatible continuum of highly integrated embedded processor devices for use in low-end to high-end intelligent IoT end-point applications. Architected for power efficiency and long battery life, these devices deliver high computation and ML/AI capability, multi-layered security, computer vision, and highly interactive human-machine interface.

Flash Banks

Flash

Flash Bank Base address Size J-Link Support
Internal flash 0x80000000 Up to 5.75 MB YES.png
OSPI flash 0xC0000000 Up to 32 MB YES.png
Note:
  • OSPI flash programming is supported for IS25WX256 only

Watchdog Handling

  • The watchdog is fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
In below, the debug related multi-core behavior of the J-Link is described for each core:

The J-Link support for the Ensemble devices includes both Cortex-M55 cores, and both Cortex-A32 cores. The user can configure the accessibility of the cores with the Alif Security Toolkit.

Example Application

The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Hilscher NetX90 evalboard. It is a simple Hello World sample linked into the internal flash. SETUP