Apollo2

SWO

On the Apollo2 series devices from Ambiq Micro, SWO is supported. However, a few device specifics apply which are described in the following.

Clock source

For most devices, the SWO clock is derived from the current MCU clock. This is not the case for the Apollo2 series devices. On these devices, the SWO clock is derived from the internal 48 MHz High Frequency RC Oscillator (HFRC).

The SWO clock provided to the CoreSight SWO/trace units is not 1:1 the speed of the HFRC, but can be configured via Apollo2 device specific registers: MCUCTRL.TPIUCTRL[CLKSEL]

CLKSEL meaning

Sub-Family	Core	J-Link Commander and J-Flash: native Unlock support	J-Link Commander: Lock via commanderfile	STM32 Unlock tool support	J-Flash: Unlock project	J-Flash: native lock support	J-Flash: Lock project
STM32F0	Cortex-M0		STM32F0_Lock.jlink		STM32F0_Unlock.jflash		STM32F0_Lock.jflash
STM32F1	Cortex-M3		STM32F1_Lock.jlink		STM32F1_Unlock.jflash		STM32F1_Lock.jflash
STM32F2	Cortex-M3		STM32F2_Lock.jlink		STM32F2_Unlock.jflash		STM32F2_Lock.jflash
STM32F3	Cortex-M4		STM32F3_Lock.jlink		STM32F3_Unlock.jflash		STM32F3_Lock.jflash
STM32F4	Cortex-M4		STM32F4_Lock.jlink		STM32F4_Unlock.jflash		STM32F4_Lock.jflash
STM32F7	Cortex-M7		STM32F7_Lock.jlink		STM32F7_Unlock.jflash		STM32F7_Lock.jflash
STM32H7	Cortex-M7	N/A	N/A		N/A		N/A
STM32L0	Cortex-M0		STM32L0_Lock.jlink		STM32L0_Unlock.jflash		STM32L0_Lock.jflash
STM32L1	Cortex-M3		STM32L1_Lock.jlink		STM32L1_Unlock.jflash		STM32L1_Lock.jflash
STM32L4	Cortex-M4		STM32L4_Lock.jlink		STM32L4_Unlock.jflash		STM32L4_Lock.jflash

Note: J-Link handles the current setting of this register automatically when calculating the SWO speed to be used.

Note: When selecting the CPU frequency in IDEs for J-Link SWO usage, select 48 MHz for the Ambiq Apollo2 series devices.