Difference between revisions of "Apollo2"
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| + | = SWO = |
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| + | On the Apollo2 series devices from Ambiq Micro, SWO is supported. However, a few device specifics apply which are described in the following. |
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| + | == Clock source == |
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| − | The STM32 Series is a popular family of Cortex-M devices by STMicroelectronics. |
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| + | For most devices, the SWO clock is derived from the current MCU clock. This is not the case for the Apollo2 series devices. On these devices, the SWO clock is derived from the internal 48 MHz High Frequency RC Oscillator (HFRC). |
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| − | The following article contains information which applies to all members of the product family (e.g. readout protection). |
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| − | Information which is more specific to the respective sub-family(e.g. QSPI programming) is provided in family specific articles. |
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| − | |||
| − | A list of all ST devices supported by SEGGER can be found [https://www.segger.com/jlink_supported_devices.html?m=ST#sel here]. |
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| − | For further information regarding the STM32 product family, please refer to the website and documentation by STMicroelectronics. |
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| − | |||
| − | = MCU Security = |
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| − | |||
| − | == Allow opt bytes device selection == |
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| − | The "allow opt. bytes" device selection is only available for STM32F1 series devices. For later devices, memory mapped programming of the option bytes is not feasible as for some series, the option bytes become valid immediately which would cause immediate connection loss to a device (in case readout protection is enabled) before the option byte programming can be verified. |
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| − | |||
| − | The STM32 series devices provide option bytes which allow "permanent" configuration as well as readout protection for the device. |
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| − | In order to enable or disable readout protection, a sequence of multiple read / write accesses to special function registers of the STM32 MCU has to be performed. |
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| − | The sequence is different for each sub-family of the STM32 device series and is described in the respective reference manual of the device. |
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| − | A list of example J-Link commander files and J-Flash projects which enable or disable the readout protection of an STM32 device is provided below. |
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| − | Please note that the provided files serves as an example / proof of concept. A user may alter them in order to suit their specific use case, e.g. using smaller timeouts, programming other values, etc. |
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| − | |||
| − | == Disabling readout protection == |
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| − | |||
| − | === J-Link Commander and J-Flash === |
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| − | J-Link Commander and J-Flash automatically detect secured STM32 devices and ask the user if it should be unlocked. Further information regarding this can be found here: [[Secured_ST_device_detected]] |
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| − | |||
| − | === Flasher standalone mode === |
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| − | In order to unlock a STM32 device in stand-alone mode, the unlock sequence needs to be configured in the init steps of the J-Flash project (see examples in the table below). |
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| − | |||
| − | === Restoring factory defaults === |
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| − | The standalone software tool STM32 Unlock can be used to reset the Option Bytes of a STM32 device to factory default settings. |
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| − | STM32 Unlock is part of the [https://www.segger.com/jlink-software.html J-Link software & documentation pack]. |
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| − | |||
| − | == Enabling readout protection == |
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| − | |||
| − | All provided J-Link Commander command files and J-Flash projects set the read out protection to level 1 (ROP == Level 1). |
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| − | In order to set ROP Level 2, the value "0xBB" needs to be changed to "0xCC" where indicated in the command file / Exit steps of the J-Flash project. |
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| − | Please note that ROP Level 2 is permanent and can neither be reverted by SEGGER nor by ST. |
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| + | The SWO clock provided to the CoreSight SWO/trace units is not 1:1 the speed of the HFRC, but can be configured via the Apollo2 device specific register '''MCUCTRL.TPIUCTRL[CLKSEL]''' |
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{| class="wikitable" |
{| class="wikitable" |
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| + | |+CLKSEL meaning |
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| − | |+STM32 series overview |
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| + | ! Value |
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| − | ! Sub-Family |
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| − | ! |
+ | ! Meaning |
| − | ! J-Link Commander and J-Flash:<br> native Unlock support |
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| − | ! J-Link Commander:<br> Lock via commanderfile |
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| − | ! STM32 Unlock tool support |
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| − | ! J-Flash:<br> Unlock project |
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| − | ! J-Flash<ref>For further information regarding native support in J-Flash and why native support is no longer implemented for new devices, please refer to this article: [[MCU_Security_Options]]</ref>:<br> native lock support |
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| − | ! J-Flash:<br> Lock project |
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|- |
|- |
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| + | |1 |
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| − | |STM32F0 |
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| + | |SWOClock == HFRC / 2 |
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| − | |Cortex-M0 |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F0_Lock.jlink | STM32F0_Lock.jlink]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F0_Unlock.jflash|STM32F0_Unlock.jflash]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F0_Lock.jflash|STM32F0_Lock.jflash]] |
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|- |
|- |
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| + | |2 |
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| − | |STM32F1 |
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| + | |SWOClock == HFRC / 8 |
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| − | |Cortex-M3 |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F1_Lock.jlink|STM32F1_Lock.jlink]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F1_Unlock.jflash|STM32F1_Unlock.jflash]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F1_Lock.jflash|STM32F1_Lock.jflash]] |
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|- |
|- |
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| + | |3 |
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| − | |STM32F2 |
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| + | |SWOClock == HFRC / 16 |
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| − | |Cortex-M3 |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F2_Lock.jlink|STM32F2_Lock.jlink]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F2_Unlock.jflash|STM32F2_Unlock.jflash]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F2_Lock.jflash|STM32F2_Lock.jflash]] |
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|- |
|- |
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| + | |4 |
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| − | |STM32F3 |
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| + | |SWOClock == HFRC / 32 |
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| − | |Cortex-M4 |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F3_Lock.jlink|STM32F3_Lock.jlink]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F3_Unlock.jflash|STM32F3_Unlock.jflash]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F3_Lock.jflash|STM32F3_Lock.jflash]] |
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| − | |- |
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| − | |[[STM32F4]] |
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| − | |Cortex-M4 |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F4_Lock.jlink|STM32F4_Lock.jlink]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F4_Unlock.jflash|STM32F4_Unlock.jflash]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F4_Lock.jflash|STM32F4_Lock.jflash]] |
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| − | |- |
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| − | |[[STM32F7]] |
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| − | |Cortex-M7 |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F7_Lock.jlink|STM32F7_Lock.jlink]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32F7_Unlock.jflash|STM32F7_Unlock.jflash]] |
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| − | |scope="col" style="text-align:center" | [[File:NO.png|20px|link=]] |
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| − | |[[:Media:STM32F7_Lock.jflash|STM32F7_Lock.jflash]] |
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| − | |- |
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| − | |STM32H7 |
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| − | |Cortex-M7 |
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| − | |N/A |
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| − | |N/A |
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| − | |scope="col" style="text-align:center" | [[File:NO.png|20px|link=]] |
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| − | |N/A |
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| − | |scope="col" style="text-align:center" | [[File:NO.png|20px|link=]] |
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| − | |N/A |
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| − | |- |
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| − | |STM32L0 |
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| − | |Cortex-M0 |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32L0_Lock.jlink|STM32L0_Lock.jlink]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32L0_Unlock.jflash|STM32L0_Unlock.jflash]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32L0_Lock.jflash|STM32L0_Lock.jflash]] |
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| − | |- |
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| − | |STM32L1 |
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| − | |Cortex-M3 |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32L1_Lock.jlink|STM32L1_Lock.jlink]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32L1_Unlock.jflash|STM32L1_Unlock.jflash]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32L1_Lock.jflash|STM32L1_Lock.jflash]] |
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| − | |- |
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| − | |[[STM32L4]] |
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| − | |Cortex-M4 |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32L4_Lock.jlink|STM32L4_Lock.jlink]] |
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| − | |scope="col" style="text-align:center" | [[File:YES.png|20px|link=]] |
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| − | |[[:Media:STM32L4_Unlock.jflash|STM32L4_Unlock.jflash]] |
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| − | |scope="col" style="text-align:center" | [[File:NO.png|20px|link=]] |
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| − | |[[:Media:STM32L4_Lock.jflash|STM32L4_Lock.jflash]] |
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|} |
|} |
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| + | '''Note:''' J-Link handles the current setting of this register automatically when calculating the SWO speed to be used. |
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| − | All command files and J-Flash projects have a specific MCU selected. |
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| + | |||
| − | For the sole purpose of locking the device via J-Link commander changing of the device name is not necessary, |
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| + | '''Note:''' When selecting the CPU frequency in IDEs for J-Link SWO usage, select 48 MHz for the Ambiq Apollo2 series devices. |
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| − | '''but it is mandatory to change the device name to the actual device used when using J-Flash or doing any flash programming in J-Link commander.''' |
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| + | |||
| + | == SWO pin == |
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| + | On the Apollo2 series devices, multiple pins are capable of being configured as SWO: |
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| + | * PAD15 |
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| + | * PAD22 |
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| + | * PAD24 |
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| + | * PAD30 |
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| + | * PAD33 |
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| + | * PAD41 |
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| + | * PAD45 |
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| + | * PAD46 |
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| + | '''Note:''' All J-Link default configurations configure and use PAD41 as SWO because this is the PAD used on the EVBs from Ambiq. |
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| − | Please note that securing a device via J-Link command files is limited in a way that interpretation of return values, |
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| − | if / else branches etc. are not available. Therefore, production programming and securing of devices can only be done with |
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| − | J-Flash or the J-Link SDK. |
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| − | In any case, it is the responsibility of the user to verify that the required read out protection is active before the programming device leaves the production facility. |
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| + | == Sample projects == |
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| − | <references/> |
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| + | Sample projects that demonstrate SWO usage are available for the following eval boards: |
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| − | //--> |
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| + | * [[Apollo2 EVB]] |
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Latest revision as of 13:20, 8 March 2018
SWO
On the Apollo2 series devices from Ambiq Micro, SWO is supported. However, a few device specifics apply which are described in the following.
Clock source
For most devices, the SWO clock is derived from the current MCU clock. This is not the case for the Apollo2 series devices. On these devices, the SWO clock is derived from the internal 48 MHz High Frequency RC Oscillator (HFRC).
The SWO clock provided to the CoreSight SWO/trace units is not 1:1 the speed of the HFRC, but can be configured via the Apollo2 device specific register MCUCTRL.TPIUCTRL[CLKSEL]
| Value | Meaning |
|---|---|
| 1 | SWOClock == HFRC / 2 |
| 2 | SWOClock == HFRC / 8 |
| 3 | SWOClock == HFRC / 16 |
| 4 | SWOClock == HFRC / 32 |
Note: J-Link handles the current setting of this register automatically when calculating the SWO speed to be used.
Note: When selecting the CPU frequency in IDEs for J-Link SWO usage, select 48 MHz for the Ambiq Apollo2 series devices.
SWO pin
On the Apollo2 series devices, multiple pins are capable of being configured as SWO:
- PAD15
- PAD22
- PAD24
- PAD30
- PAD33
- PAD41
- PAD45
- PAD46
Note: All J-Link default configurations configure and use PAD41 as SWO because this is the PAD used on the EVBs from Ambiq.
Sample projects
Sample projects that demonstrate SWO usage are available for the following eval boards:
