Difference between revisions of "Apollo2 EVB"

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= SWO =
  +
SWO is supported on the Apollo2 EVB.
   
  +
== Requirements ==
The STM32 Series is a popular family of Cortex-M devices by STMicroelectronics.
 
  +
In order to make SWO working correctly, min. J-Link software V6.30g is required. Previous versions are not guaranteed to work correctly with SWO.
The following article contains information which applies to all members of the product family (e.g. readout protection).
 
Information which is more specific to the respective sub-family(e.g. QSPI programming) is provided in family specific articles.
 
   
  +
== Pin used on MCU ==
A list of all ST devices supported by SEGGER can be found [https://www.segger.com/jlink_supported_devices.html?m=ST#sel here].
 
  +
On the Apollo2 EVB, PAD41 has been wired by Ambiq Micro as SWO output pin.
For further information regarding the STM32 product family, please refer to the website and documentation by STMicroelectronics.
 
   
= MCU Security =
+
== Sample projects ==
  +
The following sample projects that demonstrate SWO on the Apollo2 EVB are available:
   
  +
*[[Media:AmbiqMicro_Apollo2_SWO_ES340_Example.zip|Embedded Studio SWO sample project with CMSIS DFP included]]
== Allow opt bytes device selection ==
 
  +
This example project does not require any extra settings by the user. The SWO stream can be viewed with e.g. [[J-Link SWO Viewer]] which is included in the [[J-Link Software and Documentation Pack]] and is available for free. This project has been created with Embedded Studio V3.40.
The "allow opt. bytes" device selection is only available for STM32F1 series devices. For later devices, memory mapped programming of the option bytes is not feasible as for some series, the option bytes become valid immediately which would cause immediate connection loss to a device (in case readout protection is enabled) before the option byte programming can be verified.
 
   
  +
* [[Media:AmbiqMicro_Apollo2AMAPH1KK-KBR_Apollo2EVB_SWO_IAR822.zip|IAR EWARM sample project]]
The STM32 series devices provide option bytes which allow "permanent" configuration as well as readout protection for the device.
 
  +
* '''Note:''' IAR does not handle the special setup needed for this particular target device automatically so the project setting "CPU clock" must be set to CPUClock/8. Any other value will not output the SWO printf stream.
In order to enable or disable readout protection, a sequence of multiple read / write accesses to special function registers of the STM32 MCU has to be performed.
 
The sequence is different for each sub-family of the STM32 device series and is described in the respective reference manual of the device.
 
A list of example J-Link commander files and J-Flash projects which enable or disable the readout protection of an STM32 device is provided below.
 
Please note that the provided files serves as an example / proof of concept. A user may alter them in order to suit their specific use case, e.g. using smaller timeouts, programming other values, etc.
 
 
== Disabling readout protection ==
 
 
=== J-Link Commander and J-Flash ===
 
J-Link Commander and J-Flash automatically detect secured STM32 devices and ask the user if it should be unlocked. Further information regarding this can be found here: [[Secured_ST_device_detected]]
 
 
=== Flasher standalone mode ===
 
In order to unlock a STM32 device in stand-alone mode, the unlock sequence needs to be configured in the init steps of the J-Flash project (see examples in the table below).
 
 
=== Restoring factory defaults ===
 
The standalone software tool STM32 Unlock can be used to reset the Option Bytes of a STM32 device to factory default settings.
 
STM32 Unlock is part of the [https://www.segger.com/jlink-software.html J-Link software & documentation pack].
 
 
== Enabling readout protection ==
 
 
All provided J-Link Commander command files and J-Flash projects set the read out protection to level 1 (ROP == Level 1).
 
In order to set ROP Level 2, the value "0xBB" needs to be changed to "0xCC" where indicated in the command file / Exit steps of the J-Flash project.
 
Please note that ROP Level 2 is permanent and can neither be reverted by SEGGER nor by ST.
 
 
{| class="wikitable"
 
|+STM32 series overview
 
! Sub-Family
 
! Core
 
! J-Link Commander and J-Flash:<br> native Unlock support
 
! J-Link Commander:<br> Lock via commanderfile
 
! STM32 Unlock tool support
 
! J-Flash:<br> Unlock project
 
! J-Flash<ref>For further information regarding native support in J-Flash and why native support is no longer implemented for new devices, please refer to this article: [[MCU_Security_Options]]</ref>:<br> native lock support
 
! J-Flash:<br> Lock project
 
|-
 
|STM32F0
 
|Cortex-M0
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F0_Lock.jlink | STM32F0_Lock.jlink]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F0_Unlock.jflash|STM32F0_Unlock.jflash]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F0_Lock.jflash|STM32F0_Lock.jflash]]
 
|-
 
|STM32F1
 
|Cortex-M3
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F1_Lock.jlink|STM32F1_Lock.jlink]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F1_Unlock.jflash|STM32F1_Unlock.jflash]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F1_Lock.jflash|STM32F1_Lock.jflash]]
 
|-
 
|STM32F2
 
|Cortex-M3
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F2_Lock.jlink|STM32F2_Lock.jlink]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F2_Unlock.jflash|STM32F2_Unlock.jflash]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F2_Lock.jflash|STM32F2_Lock.jflash]]
 
|-
 
|STM32F3
 
|Cortex-M4
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F3_Lock.jlink|STM32F3_Lock.jlink]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F3_Unlock.jflash|STM32F3_Unlock.jflash]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F3_Lock.jflash|STM32F3_Lock.jflash]]
 
|-
 
|[[STM32F4]]
 
|Cortex-M4
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F4_Lock.jlink|STM32F4_Lock.jlink]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F4_Unlock.jflash|STM32F4_Unlock.jflash]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F4_Lock.jflash|STM32F4_Lock.jflash]]
 
|-
 
|[[STM32F7]]
 
|Cortex-M7
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F7_Lock.jlink|STM32F7_Lock.jlink]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32F7_Unlock.jflash|STM32F7_Unlock.jflash]]
 
|scope="col" style="text-align:center" | [[File:NO.png|20px|link=]]
 
|[[:Media:STM32F7_Lock.jflash|STM32F7_Lock.jflash]]
 
|-
 
|STM32H7
 
|Cortex-M7
 
|N/A
 
|N/A
 
|scope="col" style="text-align:center" | [[File:NO.png|20px|link=]]
 
|N/A
 
|scope="col" style="text-align:center" | [[File:NO.png|20px|link=]]
 
|N/A
 
|-
 
|STM32L0
 
|Cortex-M0
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32L0_Lock.jlink|STM32L0_Lock.jlink]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32L0_Unlock.jflash|STM32L0_Unlock.jflash]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32L0_Lock.jflash|STM32L0_Lock.jflash]]
 
|-
 
|STM32L1
 
|Cortex-M3
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32L1_Lock.jlink|STM32L1_Lock.jlink]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32L1_Unlock.jflash|STM32L1_Unlock.jflash]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32L1_Lock.jflash|STM32L1_Lock.jflash]]
 
|-
 
|[[STM32L4]]
 
|Cortex-M4
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32L4_Lock.jlink|STM32L4_Lock.jlink]]
 
|scope="col" style="text-align:center" | [[File:YES.png|20px|link=]]
 
|[[:Media:STM32L4_Unlock.jflash|STM32L4_Unlock.jflash]]
 
|scope="col" style="text-align:center" | [[File:NO.png|20px|link=]]
 
|[[:Media:STM32L4_Lock.jflash|STM32L4_Lock.jflash]]
 
|}
 
 
All command files and J-Flash projects have a specific MCU selected.
 
For the sole purpose of locking the device via J-Link commander changing of the device name is not necessary,
 
'''but it is mandatory to change the device name to the actual device used when using J-Flash or doing any flash programming in J-Link commander.'''
 
 
Please note that securing a device via J-Link command files is limited in a way that interpretation of return values,
 
if / else branches etc. are not available. Therefore, production programming and securing of devices can only be done with
 
J-Flash or the J-Link SDK.
 
In any case, it is the responsibility of the user to verify that the required read out protection is active before the programming device leaves the production facility.
 
 
<references/>
 
//-->
 

Latest revision as of 12:18, 17 July 2020

SWO

SWO is supported on the Apollo2 EVB.

Requirements

In order to make SWO working correctly, min. J-Link software V6.30g is required. Previous versions are not guaranteed to work correctly with SWO.

Pin used on MCU

On the Apollo2 EVB, PAD41 has been wired by Ambiq Micro as SWO output pin.

Sample projects

The following sample projects that demonstrate SWO on the Apollo2 EVB are available:

This example project does not require any extra settings by the user. The SWO stream can be viewed with e.g. J-Link SWO Viewer which is included in the J-Link Software and Documentation Pack and is available for free. This project has been created with Embedded Studio V3.40.

  • IAR EWARM sample project
  • Note: IAR does not handle the special setup needed for this particular target device automatically so the project setting "CPU clock" must be set to CPUClock/8. Any other value will not output the SWO printf stream.