Difference between revisions of "Arm trace technical specification"

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[[File:trace_clock.png | thumb | none | 600px | Trace timing diagram with CPU clock, TRACECLK and Trace data]]
 
[[File:trace_clock.png | thumb | none | 600px | Trace timing diagram with CPU clock, TRACECLK and Trace data]]
 
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Revision as of 15:20, 22 September 2022

When using the J-Trace PRO as a debugging tool it is crucial for a successful session that the trace data output by the microcontroller is meeting specific timing requirements. The trace clock speed (TRACECLK) is on most microcontrollers directly dependent on the CPU clock speed and is usually half of the CPU clock speed.

Arm trace timing requirements

Arm defines the trace timing requirements as follows:

Trace timing diagram with CPU clock, TRACECLK and Trace data
Timing variables and values
Signal name Description Value
twl TRACECLK LOW pulse width Min. 2 ns
twh TRACECLK HIGH pulse width Min. 2 ns
tr/tf Clock and data rise/fall time Max. 3 ns
ts Data setup time Min. 3 ns
th Data hold time Min. 2 ns