Difference between revisions of "CMSemicon BAT32G133"

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(Option Bytes)
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__TOC__
 
__TOC__
The BAT32G1xxGx series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M0 processor.
+
The BAT32G133 series (BAT32 family) are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M0 processor.
 
==Internal ECC RAM==
 
==Internal ECC RAM==
 
{| class="seggertable"
 
{| class="seggertable"
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! Device || StartAddr !! Size
 
! Device || StartAddr !! Size
 
|-
 
|-
| BAT32G133xAxxxx || 0x20000000 || 4Kb
+
| BAT32G133GC20NB || 0x20000000 || 4 KB
 
|-
 
|-
| BAT32G133xCxxxx || 0x20000000 || 4Kb
+
| BAT32G133GC20SA || 0x20000000 || 4 KB
 
|-
 
|-
| BAT32G157xHxxxx || 0x20000000 || 32Kb
+
| BAT32G133GC24NA || 0x20000000 || 4 KB
 
|-
 
|-
| BAT32G157xKxxxx || 0x20000000 || 32Kb
+
| BAT32G133GC24SS || 0x20000000 || 4 KB
 
|}
 
|}
   
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! Device || StartAddr !! Size || J-Link Support
 
! Device || StartAddr !! Size || J-Link Support
 
|-
 
|-
| BAT32G133xAxxxx || 0x00000000 || 16Kb || YES
+
| BAT32G133GC20NB || 0x00000000 || 32 KB || YES
 
|-
 
|-
| BAT32G133xCxxxx || 0x00000000 || 32Kb || YES
+
| BAT32G133GC20SA || 0x00000000 || 32 KB || YES
 
|-
 
|-
| BAT32G157xHxxxx || 0x08000000 || 128Kb || YES
+
| BAT32G133GC24NA || 0x00000000 || 32 KB || YES
 
|-
 
|-
| BAT32G157xKxxxx || 0x08000000 || 256Kb || YES
+
| BAT32G133GC24SS || 0x00000000 || 32 KB || YES
 
|}
 
|}
   
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! Device || StartAddr !! Size || J-Link Support
 
! Device || StartAddr !! Size || J-Link Support
 
|-
 
|-
| BAT32G133xAxxxx || 0x00500000 || 1.5Kb || YES
+
| BAT32G133GC20NB || 0x00500000 || 1.5 KB || YES
 
|-
 
|-
| BAT32G133xCxxxx || 0x00500000 || 1.5Kb || YES
+
| BAT32G133GC20SA || 0x00500000 || 1.5 KB || YES
 
|-
 
|-
| BAT32G157xHxxxx || 0x08500200 || 2.5Kb || YES
+
| BAT32G133GC24NA || 0x00500000 || 1.5 KB || YES
 
|-
 
|-
| BAT32G157xKxxxx || 0x08500200 || 2.5Kb || YES
+
| BAT32G133GC24SS || 0x00500000 || 1.5 KB || YES
 
|}
 
|}
 
   
 
===Option Bytes ===
 
===Option Bytes ===
Within the Flash-Area (Offset:0x0c) and DataFlash-Area (Offset:0x4)
+
Within this flash area (offset: 0x0C) and data flash (offset: 0x4)
   
 
Please refer to the manual for detailed description
 
Please refer to the manual for detailed description
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|}
 
|}
   
  +
AS THE OPTION BYTES ARE WITHIN THE NORMAL FLASH AREA PLEASE ENSURE NOT TO OVERWRITE WITH PROGRAM CODE<br>
 
  +
{{Note|AS THE OPTION BYTES ARE WITHIN THE NORMAL FLASH AREA PLEASE ENSURE NOT TO OVERWRITE WITH PROGRAM CODE<br>
ONE POSSIBLE SOLUTION IS WITHIN THE EXAMPLES
 
  +
ONE POSSIBLE SOLUTION IS WITHIN THE EXAMPLES}}
   
 
==Reset==
 
==Reset==
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==Minimum requirements==
 
==Minimum requirements==
* J-Link software V7.__b or later
+
* J-Link software V7.82c or later
   
 
==Evaluation Boards==
 
==Evaluation Boards==
*CMSemicon BAT32G133-EVB evaluation board: https://wiki.segger.com/CMSemicon_BAT32G1xx_EVB
+
*CMSemicon BAT32G133-EVB evaluation board: https://wiki.segger.com/CMSemicon_BAT32G133-EVB
 
==Example Application==
 
*CMSemicon BAT32G133-EVB evaluation board: https://wiki.segger.com/CMSemicon_BAT32G1xx_EVB#Example_Project
 

Latest revision as of 15:11, 14 November 2022

The BAT32G133 series (BAT32 family) are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M0 processor.

Internal ECC RAM

Device StartAddr Size
BAT32G133GC20NB 0x20000000 4 KB
BAT32G133GC20SA 0x20000000 4 KB
BAT32G133GC24NA 0x20000000 4 KB
BAT32G133GC24SS 0x20000000 4 KB
  *** Additional information ***

In order to prevent errors when reading first time, the DLL intialises the first 4Kb of RAM starting at 0x2000_0000.
Due to this attaching to a running system is not possible.

Supported Flash Banks

Internal Flash

Device StartAddr Size J-Link Support
BAT32G133GC20NB 0x00000000 32 KB YES
BAT32G133GC20SA 0x00000000 32 KB YES
BAT32G133GC24NA 0x00000000 32 KB YES
BAT32G133GC24SS 0x00000000 32 KB YES

Internal Data Flash

Device StartAddr Size J-Link Support
BAT32G133GC20NB 0x00500000 1.5 KB YES
BAT32G133GC20SA 0x00500000 1.5 KB YES
BAT32G133GC24NA 0x00500000 1.5 KB YES
BAT32G133GC24SS 0x00500000 1.5 KB YES

Option Bytes

Within this flash area (offset: 0x0C) and data flash (offset: 0x4)

Please refer to the manual for detailed description

Offset Register
0xc0 WDT Control BYTE
0xc1 LVD Control BYTE (C1H)
0xc2 HOCO Control BYTE (FRQSEL)
0xc3 Flash Protect Control BYTE
0xc4 Boot Area Control BYTE
0xc5 QSPI flash protect option BYTE
0xc6 QSPI flash protect option BYTE0
0xc7 QSPI flash protect option BYTE1


Note:

AS THE OPTION BYTES ARE WITHIN THE NORMAL FLASH AREA PLEASE ENSURE NOT TO OVERWRITE WITH PROGRAM CODE

ONE POSSIBLE SOLUTION IS WITHIN THE EXAMPLES

Reset

The device uses normal reset, no special handling necessary.

Minimum requirements

  • J-Link software V7.82c or later

Evaluation Boards