Codasip L10

From SEGGER Wiki
Revision as of 13:22, 10 June 2021 by Alex (talk | contribs) (Created page with "The Codasip L10 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. __TOC__ = Minimum required J-Link software version =...")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

The Codasip L10 is a 32-bit (RV32) core, designed by Codasip.

Minimum required J-Link software version

The L10 device selection is supported since V7.24 of the J-Link software.

RTT support

As the core does not support System Bus Access (SBA), RTT is not supported for this core.

HSS access

As the core does not support System Bus Access (SBA), HSS is not supported for this core.