Codasip L30

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Revision as of 13:22, 10 June 2021 by Alex (talk | contribs) (Created page with "The Codasip L30 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. It is available in 2 variants: * L30 (no FPU) * L30F (i...")
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The Codasip L30 is a 32-bit (RV32) core, designed by Codasip. It is available in 2 variants:

  • L30 (no FPU)
  • L30F (incl. FPU)

Minimum required J-Link software version

The L30 / L30F device selection is supported since V7.24 of the J-Link software.

RTT support

As the core does not support System Bus Access (SBA), RTT is not supported for this core.

HSS access

As the core does not support System Bus Access (SBA), HSS is not supported for this core.