Difference between revisions of "Infineon CYT2BL"

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'''CYT2BL (TVII-B-E-4M)''' is a subfamily of Traveo II microcontrollers containing a Cortex M4 and Cortex M0+ CPU.
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'''CYT2BL (TVII-B-E-4M)''' is a subfamily of [[Cypress Traveo II device family | Traveo II]] microcontrollers containing a Cortex M4 and Cortex M0+ CPU.
   
 
== Flash memory layout ==
 
== Flash memory layout ==

Revision as of 14:29, 31 March 2021

CYT2BL (TVII-B-E-4M) is a subfamily of Traveo II microcontrollers containing a Cortex M4 and Cortex M0+ CPU.

Flash memory layout

The CYT2BL series devices have 4160 KB Code flash and a 128 KB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.

Flash Start adress End adress Sector size Sector count Total size
Code flash large area 0x10000000 0x103EFFFF 32 KB 126 4032 KB
Code flash small area 0x103F0000 0x1040FFFF 8 KB 16 128 KB
Work flash large area 0x14000000 0x14017FFF 2 KB 48 96 KB
Work flash small area 0x14018000 0x1401FFFF 128 B 256 32 KB