Difference between revisions of "Infineon CYT4BF"

From SEGGER Wiki
Jump to: navigation, search
(Created page with "'''CYT4BF (TVII-B-H-8M)''' is a subfamily of Traveo II microcontrollers containing a Cortex M7 and Cortex M0+ CPU. == Flash memory layout == The CYT4BF series devices have 8...")
 
Line 1: Line 1:
'''CYT4BF (TVII-B-H-8M)''' is a subfamily of Traveo II microcontrollers containing a Cortex M7 and Cortex M0+ CPU.
+
'''CYT4BF (TVII-B-H-8M)''' is a subfamily of [[Cypress Traveo II device family | Traveo II]] microcontrollers containing a Cortex M7 and Cortex M0+ CPU.
   
 
== Flash memory layout ==
 
== Flash memory layout ==

Revision as of 14:29, 31 March 2021

CYT4BF (TVII-B-H-8M) is a subfamily of Traveo II microcontrollers containing a Cortex M7 and Cortex M0+ CPU.

Flash memory layout

The CYT4BF series devices have 8384 KB Code flash and a 256 KB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.

Flash Start adress End adress Sector size Sector count Total size
Code flash large area 0x10000000 0x107EFFFF 32 KB 254 8128 KB
Code flash small area 0x107F0000 0x1082FFFF 8 KB 32 256 KB
Work flash large area 0x14000000 0x1402FFFF 2 KB 96 192 KB
Work flash small area 0x14030000 0x1403FFFF 128 B 512 64 KB