DAP

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The debug access port (DAP) means the DP and all APs that are connected to the DP. It is to describe the whole debug hierarchy. It was initially designed as a standard to enable debug access to ARM cores but has been developed to a standard that also allows to access ARM and non-ARM cores in the same design via a single debug connector, all sharing the same pins on the device. This enables silicon vendors to easily create hybrid devices that contain ARM and non-ARM cores in the same design and which only expose a single standardized debug interface that allows debug access to all of the cores in the device.

DP

The debug port (DP) translates from the physical protocol that is used to communicate with the debug logic to the ARM specific internal debug logic. There are different types of DPs:

  • JTAG-DP
  • SW-DP
  • SWJ-DP

There is only one DP in a DAP.

JTAG-DP

JTAG is used to exchange information with the debug logic. The physical protocol may be 4-wire JTAG (IEEE 1149.1) or 2-wire cJTAG (IEEE 1149.7).

cJTAG and DP

Device internally, the DP understands 4-wire JTAG only. In case externally cJTAG is used as the physical protocol, there is a device internal 2-to-4-wire converter unit in front of the JTAG-DP that translates from cJTAG to JTAG. The DP still sees 4 signals internally, but only 2 are physically available at the pins of the MCU.

SW-DP

2-wire Serial Wire Debug (SWD) is used to exchange information with the debug logic.

SWJ-DP

JTAG or SWD may be used to exchange information with the debug logic. The protocol is switched between JTAG and SWD at runtime, using specific switching sequences that are specified by ARM and do not hurt JTAG devices that may be in the same JTAG chain as the SWJ-DP.

AP

A access port (AP) mainly is a memory bus interface to access the actual debug logic / resources. While the DP performs the protocol translation, an AP usually performs real memory accesses to read/write debug register. APs are comparable to DMAs and allow to issue memory accesses without using the CPU core. There are different types of APs:

  • AHB-AP
  • APB-AP
  • AXI-AP
  • JTAG-AP

While there is only one DP in a DAP system, multiple APs may be connected to a single DP.

AHB-AP

This was the first AP type to be introduced and was first used on Cortex-M based targets. The AHB-AP acts like a second memory interface to the system memory and debug registers of the CPU core. In this setup, the AHB-AP and the CPU core share the same 4 GB address space. This means, the debug registers are accessible via the debug interface as well as from the CPU core itself. A nice side effect of this setup is that the AHB-AP allows reading / writing the system memory (RAM, SFRs, ...) independent from the core (like a DMA). This allows techniques like SEGGER RTT to be used.

APB-AP

TBD

AXI-AP

TBD

JTAG-AP

TBD

DAP topology Cortex-M

TBD

DAP topology Cortex-A

TBD

DAP topology Cortex-R

See DAP topology Cortex-A

DAP topology Xtensa

TBD

DAP topology RISC-V

TBD