Difference between revisions of "Debug Probes - J-Link & J-Trace"

From SEGGER Wiki
Jump to: navigation, search
(→‎Device Specifics)
Line 43: Line 43:
 
* [[Setting up Ethernet interface]]
  
* [[Setting up Ethernet interface]]
 
* [[CFI Flash]]
  
* [[CFI Flash]]
−
* [[J-Link:Nickname | Nickname feature]]
 +
* [[J-Link Nickname | Nickname feature]]
 
* [[J-Link_Docker_Container | J-Link in a Docker Container]]
  
* [[J-Link_Docker_Container | J-Link in a Docker Container]]
 
* [[How to use SWO with GDB | How to use SWO with J-Link GDB Server]]
  
* [[How to use SWO with GDB | How to use SWO with J-Link GDB Server]]
Line 55: Line 55:
 
* [[J-Trace PRO Cortex]]
  
* [[J-Trace PRO Cortex]]
 
* [[J-Link-OB-K22-SiFive | J-Link OB K22 SiFive]]
  
* [[J-Link-OB-K22-SiFive | J-Link OB K22 SiFive]]
−
* [https://wiki.segger.com/J-Link:OEM_models OEM models overview].
 +
* [https://wiki.segger.com/J-Link_OEM_models OEM models overview].
   
 
=== Extending device support ===
  
=== Extending device support ===
Line 80: Line 80:
 
* [[J-Link application not starting]]
  
* [[J-Link application not starting]]
 
* [[IDE accesses illegal memory regions]]
  
* [[IDE accesses illegal memory regions]]
−
* [[J-Link:Low power modes production | Low power modes production]]
 +
* [[J-Link Low power modes production | Low power modes production]]
 
* [[J-Trace driver (WinUSB) is installed but the driver could not be started]]
  
* [[J-Trace driver (WinUSB) is installed but the driver could not be started]]
   
Line 95: Line 95:
   
 
==== AndesTech ====
  
==== AndesTech ====
−
* [[J-Link:AndesTech A25 | A25 (RISC-V)]]
 +
* [[J-Link AndesTech A25 | A25 (RISC-V)]]
   
 
==== ARM ====
  
==== ARM ====
Line 183: Line 183:
   
 
==== Renesas ====
  
==== Renesas ====
−
* [[J-Link:Renesas_RA6M3 | RA6M3]]
 +
* [[J-Link Renesas_RA6M3 | RA6M3]]
 
* [[Renesas_RE01 | RE01]]
  
* [[Renesas_RE01 | RE01]]
 
* [[RZ/G1]]
  
* [[RZ/G1]]
Line 239: Line 239:
   
 
=== Core specifics ===
  
=== Core specifics ===
−
* [[J-Link:RISC-V | RISC-V]]
 +
* [[J-Link RISC-V | RISC-V]]
   
 
=== Evaluation board specifics ===
  
=== Evaluation board specifics ===
Line 342: Line 342:
 
* [[How to configure JLinkScript files to enable tracing]]
  
* [[How to configure JLinkScript files to enable tracing]]
 
* [[Getting unknown addresses in instruction trace]]
  
* [[Getting unknown addresses in instruction trace]]
−
* [[J-Link:SiFive Insight | SiFive Insight]]
 +
* [[J-Link SiFive Insight | SiFive Insight]]
 
=== Device Specifics ===
  
=== Device Specifics ===
 
* [[Tracing on Atmel ATSAMA5D2]]
  
* [[Tracing on Atmel ATSAMA5D2]]
Line 424: Line 424:
   
 
== WebUSB ==
  
== WebUSB ==
−
* [[J-Link:WebUSB | Application programming via WebUSB]]
 +
* [[J-Link WebUSB | Application programming via WebUSB]]
   
 
== [[J-Flash]] ==
  
== [[J-Flash]] ==
Line 455: Line 455:
 
*[[SEGGER Ozone#Start_debug_session_with_bootloader|Watch window expression examples]]
  
*[[SEGGER Ozone#Start_debug_session_with_bootloader|Watch window expression examples]]
 
== TIF specifics ==
  
== TIF specifics ==
−
* [[J-Link:cJTAG specifics | cJTAG specifics]]
 +
* [[J-Link cJTAG specifics | cJTAG specifics]]
   
 
== FAQ ==
  
== FAQ ==

Revision as of 13:43, 5 June 2020

The J-Link debug probes with their outstanding performance, robustness, and ease of use are the market leading debug probes today. The J-Trace PRO sets a benchmark for instruction tracing with its streaming trace function that enables unlimited tracing at full clock speed.

This wiki page explains and links to details and device specifics that can not be found on the debug and trace probes product pages.

Glossary / Definitions of Debug and Trace specific terms

J-Link

SEGGER J-Links are the most widely used line of debug probes available today. They've proven their value for more than 10 years in embedded development. This popularity stems from the unparalleled performance, extensive feature set, large number of supported CPUs, and compatibility with all popular development environments.

J-Link software

J-Link model specifics

For an overview which hardware versions of the different models support which features, please refer to the model feature overview.

Extending device support

Troubleshooting

Device specifics

Altera

Ambiq Micro

Analog Devices

AndesTech

ARM

Atmel

Cypress

China Key System (CKS)

Dialog Semiconductor

GigaDevice

Infineon

Intel

MediaTek

Microchip

Nordic Semi

Nuvoton

NXP

Qorvo

Renesas

Silicon Labs

SiFive

ST

Syntacore

TI

Toshiba

Xilinx

Zilog

Core specifics

Evaluation board specifics

ARM

Ambiq Micro

Adafruit

Atmel

GigaDevice

Infineon

MediaTek

Microchip

Nordic Semiconductor

Nuvoton

NXP

Renesas

SiFive

Silicon Labs

Syntacore

STM32Duino

TI

ST

Xilinx

Flash programming

J-Trace

J-Trace PRO is an advanced debug probe that supports the advanced tracing features of Arm Cortex cores. It can capture complete instruction traces over long periods of time—thereby enabling the recording of infrequent, hard-to-reproduce bugs. This is particularly helpful when the program flow "runs off the rails" and stops in a fault state. Using the right software tools, J-Trace PRO trace probes are particularly helpful in analyzing system behaviour enabling uninstrumented live code coverage and code profiling.

Device Specifics

Keil MDK

RTT

WebUSB

J-Flash

J-Flash SPI

IDE and Debugger specifics

Ozone

TIF specifics

FAQ

Glossary / Definitions

Retrieved from "https://wiki.segger.com/index.php?title=Debug_Probes_-_J-Link_%26_J-Trace&oldid=8069"