Difference between revisions of "EFR32"
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| + | #REDIRECT [[Debug Probes - J-Link & J-Trace#Silicon Labs]] |
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| − | This article covers the Silicon Labs (SiLabs) EFR32 series device. |
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| − | __TOC__ |
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| − | = EFR32MG21xxx family = |
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| − | The SiLabs EFR32MG21xxx are Cortex-M33 MCUs. |
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| − | == Tracing on EFR32MG21xxx series == |
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| − | This section describes how to get started with trace on the SiLabs EFR32MG21xxx MCUs. |
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| − | This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). |
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| − | If this is not the case, we recommend to read '''Trace''' chapter in the J-Link User Manual (UM08001). |
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| − | '''Note:''' |
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| − | * The sample projects come with a pre-configured project file for Ozone that runs out-of-the box. |
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| − | * The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace. |
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| − | * In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used. |
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| − | * All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source it can be requested at [mailto:support@segger.com support@segger.com]. |
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| − | * The EFR32MG21xxx device only support 1-bit tracing (1-pin trace). Therefore, overflows can happen when tracing this chip.<br>Keep in mind: The higher the MCU clock speed, the higehr is the chance to get overflows. |
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| − | * In future, a stalling mode version of the project will be added, using ARM stalling mode to halt the MCU in case of an overflow.<br>Please note, that any kind of stalling mode will affect the real time behavior. |
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| − | === Tracing on SiLabs EFR32MGM210 (SiLabs Wireless Gecko xGM210P022) === |
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| − | ==== Minimum requirements ==== |
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| − | In order to use trace on the ST EFR32MGM210 MCU devices, the following minimum requirements have to be met: |
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| − | * J-Link software version V6.64c or later |
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| − | * Ozone V3.10f or later (if streaming trace and / or the sample project from below shall be used) |
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| − | * J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace |
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| − | ==== Streaming trace ==== |
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| − | The project has been tested with the minimum requirements mentioned above and a ''SiLabs Wireless Gecko xGM210P022'' which can be purchased on the SEGGER Website. |
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| − | '''Example project:''' [[Media:SiLabs_EFR32MG21_TracePin.zip | SiLabs_EFR32MG21_TracePin.zip]] |
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| − | ==== Reference trace signal quality ==== |
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| − | The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
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| − | All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. |
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| − | If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. |
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| − | More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
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| − | ===== Trace clock signal quality ===== |
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| − | The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
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| − | [[File:SiLabs_EFR32MGM21_Multiple_TCLK.png|none|thumb|Trace clock signal quality]] |
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| − | ===== Rise time ===== |
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| − | The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. |
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| − | For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
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| − | [[File:SiLabs_EFR32MGM21_Risetime_TCLK.png|none|thumb|TCLK rise time]] |
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| − | ===== Setup time ===== |
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| − | The setup time shows the relative setup time between a trace data signal and trace clock. |
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| − | The measurement markers are set at 50% of the expected voltage level respectively. |
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| − | The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal. |
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| − | [[File:SiLabs_EFR32MGM21_Setuptime_TD0.png|none|thumb|TD0 setup time]] |
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Latest revision as of 12:51, 19 October 2021
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