Difference between revisions of "EFR32"
(→Tracing on SiLabs EFR32MGM210 (SiLabs Wireless Gecko xGM210P022)) |
(Redirected page to Debug Probes - J-Link & J-Trace#Silicon Labs) (Tag: New redirect) |
||
(6 intermediate revisions by 3 users not shown) | |||
Line 1: | Line 1: | ||
+ | #REDIRECT [[Debug Probes - J-Link & J-Trace#Silicon Labs]] |
||
− | This article covers the Silicon Labs (SiLabs) EFR32 series device. |
||
− | |||
− | __TOC__ |
||
− | |||
− | = EFR32MG21xxx family = |
||
− | The SiLabs EFR32MG21xxx are Cortex-M33 MCUs. |
||
− | |||
− | == Tracing on EFR32MG21xxx series == |
||
− | This section describes how to get started with trace on the SiLabs EFR32MG21xxx MCUs. |
||
− | This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). |
||
− | If this is not the case, we recommend to read '''Trace''' chapter in the J-Link User Manual (UM08001). |
||
− | |||
− | '''Note:''' |
||
− | * The sample projects come with a pre-configured project file for Ozone that runs out-of-the box. |
||
− | * The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace. |
||
− | * In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used. |
||
− | * All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source it can be requested at [mailto:support@segger.com support@segger.com]. |
||
− | * The EFR32MG21xxx device only support 1-bit tracing (1-pin trace). Therefore, overflows can happen when tracing this chip.<br>Keep in mind: The higher the MCU clock speed, the higehr is the chance to get overflows. |
||
− | * In future, a stalling mode version of the project will be added, using ARM stalling mode to halt the MCU in case of an overflow.<br>Please note, that any kind of stalling mode will affect the real time behavior. |
||
− | |||
− | === Tracing on SiLabs EFR32MG21xxx//EFR32MGM21xxx (SiLabs Wireless Gecko xGM210P022) === |
||
− | ==== Minimum requirements ==== |
||
− | In order to use trace on the ST EFR32MGM210 MCU devices, the following minimum requirements have to be met: |
||
− | * J-Link software version V6.64c or later |
||
− | * Ozone V3.10f or later (if streaming trace and / or the sample project from below shall be used) |
||
− | * J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace |
||
− | |||
− | ==== Streaming trace ==== |
||
− | The project has been tested with the minimum requirements mentioned above and a ''SiLabs Wireless Gecko xGM210P022'' which can be purchased on the SEGGER Website. |
||
− | |||
− | '''Example project:''' [[Media:SiLabs_EFR32MG21_TracePins.zip | SiLabs_EFR32MG21_TracePins.zip]] |
||
− | |||
− | ==== Reference trace signal quality ==== |
||
− | The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
||
− | All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. |
||
− | If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. |
||
− | More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
||
− | |||
− | ===== Trace clock signal quality ===== |
||
− | The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
||
− | [[File:SiLabs_EFR32MGM21_Multiple_TCLK.png|none|thumb|Trace clock signal quality]] |
||
− | ===== Rise time ===== |
||
− | The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. |
||
− | For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
||
− | [[File:SiLabs_EFR32MGM21_Risetime_TCLK.png|none|thumb|TCLK rise time]] |
||
− | |||
− | ===== Setup time ===== |
||
− | The setup time shows the relative setup time between a trace data signal and trace clock. |
||
− | The measurement markers are set at 50% of the expected voltage level respectively. |
||
− | The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal. |
||
− | [[File:SiLabs_EFR32MGM21_Setuptime_TD0.png|none|thumb|TD0 setup time]] |
||
− | |||
− | = EFR32xG1x family= |
||
− | == Bootloader == |
||
− | On EFR32xG1x series devices, a bootloader is executed after reset. The bootloader is stored in a separate section in the ''Information'' memory space of the device. The section is called ''Bootloader (BL)'' and located at memory address 0x0FE10000. The size depends on the device. Factory-fresh devices are pre-programmed with a simple bootloader which jumps to the start of the internal flash. However, customers are allowed to exchange the bootloader with a customized one which supports more complex tasks like SPI flash, crypto, etc... Therefore, the J-Link software supports erasing as well as programming of this section. |
||
− | |||
− | === Problem === |
||
− | When issueing a chip erase, the bootloader section and therefore the bootloader will be erased as well. As a result, the device will no longer boot as no valid bootloader resides in the bootloader section. |
||
− | |||
− | === Solution === |
||
− | Below, two different solutions are presented. Apart from this, the J-Link software may be adapted in the future to not erase the bootloader section by default. |
||
− | #Do not perform a chip erase. Basically a separate is not necessary as the J-Link software always performs an implicit erase prior programming if required. |
||
− | #Program the bootloader (see '''Files''' below) as part of the application or in a separate step after programming the application |
||
− | |||
− | === Files === |
||
− | * [[:File:Dummy_btl_efr32xg1x.mot | EFR32xG1x default bootloader]] |
Latest revision as of 11:51, 19 October 2021
Redirect to: