Difference between revisions of "GigaDevice GD32A5"

From SEGGER Wiki
Jump to: navigation, search
(Internal Flash)
 
(19 intermediate revisions by the same user not shown)
Line 1: Line 1:
  +
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm®
  +
Cortex®-M33 processor.
 
__TOC__
 
__TOC__
  +
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm®
 
  +
==Flash Banks==
Cortex®-M33 processor.<br>
 
==Internal RAM==
+
===Internal Flash===
 
{| class="seggertable"
 
{| class="seggertable"
 
|-
 
|-
! Device || StartAddr !! Size
+
! Flash Bank || Base address !! Size || J-Link Support
 
|-
 
|-
  +
| Main flash Bank 0 || 0x08000000 || Up to 256 KB || style="text-align:center;"| {{YES}}
| GD32A503xB || 0x20000000 || 24Kb
 
 
|-
 
|-
  +
| Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}}
| GD32A503xC || 0x20000000 || 32Kb
 
 
|-
 
|-
  +
| Data flash || 0x08800000 || up to 64 KB || style="text-align:center;"| {{NO}}
| GD32A503xD || 0x20000000 || 48Kb
 
|}
 
 
 
==Supported Flash Banks==
 
===Internal Flash===
 
{| class="seggertable"
 
 
|-
 
|-
  +
| Option Byte 0 || 0x1FFFF800 || 24 B || style="text-align:center;"| {{YES}}
! Device || StartAddr !! Size || J-Link Support
 
 
|-
 
|-
  +
| Option Byte 1 || 0x4002 2068|| 4 B || style="text-align:center;"| {{NO}}
| GD32A503xB || 0x08000000 || 128Kb || YES
 
 
|-
 
|-
  +
| OTP Bytes || 0x1FFF7000 || 1 KB || style="text-align:center;"| {{NO}}
| GD32A503xC || 0x08000000 || 256Kb || YES
 
|-
 
| GD32A503xD || 0x08000000 || 384Kb || YES
 
 
|}
 
|}
   
  +
==ECC RAM==
  +
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM
  +
starting at 0x2000 0000.
  +
  +
==Watchdog Handling==
  +
*The device does have 2 watchdogs.
  +
*The watchdogs are fed during flash programming.
  +
  +
==Device Specific Handling==
  +
===Connect===
  +
* On Connect, protection level is checked. For further information regarding this, please click [[GigaDevice_GD32| here]].
  +
  +
===Reset===
  +
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
   
===Option Byte ===
 
{| class="seggertable"
 
|-
 
! Device || StartAddr !! Size || J-Link Support
 
|-
 
| GD32A503xB || 0x1FFFF800 || 24 Byte || YES
 
|-
 
| GD32A503xC || 0x1FFFF800 || 24 Byte|| YES
 
|-
 
| GD32A503xD || 0x1FFFF800 || 24 Byte|| YES
 
|}
 
==Reset==
 
The device uses normal reset, no special handling necessary.
 
===ECC RAM===
 
In order to prevent errors when reading first time, the DLL intialises the first 24Kb of RAM
 
starting at 0x2000 0000.
 
 
==Evaluation Boards==
 
==Evaluation Boards==
  +
*[[GigaDevice_GD32A503-EVAL|GigaDevice GD32A503-EVAL]]
*#### evaluation board: https://wiki.segger.com/####
 
   
 
==Example Application==
 
==Example Application==
  +
*[[GigaDevice_GD32A503-EVAL#Example_Project | GigaDevice GD32A503-EVAL]]
*##### evaluation board: https://wiki.segger.com/######Example_Project
 

Latest revision as of 15:27, 16 February 2024

The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M33 processor.

Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support
Main flash Bank 0 0x08000000 Up to 256 KB YES.png
Main flash Bank 1 0x08040000 128 KB YES.png
Data flash 0x08800000 up to 64 KB NO.png
Option Byte 0 0x1FFFF800 24 B YES.png
Option Byte 1 0x4002 2068 4 B NO.png
OTP Bytes 0x1FFF7000 1 KB NO.png

ECC RAM

In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM starting at 0x2000 0000.

Watchdog Handling

  • The device does have 2 watchdogs.
  • The watchdogs are fed during flash programming.

Device Specific Handling

Connect

  • On Connect, protection level is checked. For further information regarding this, please click here.

Reset

  • The device uses normal Cortex-M reset, no special handling necessary, like described here.

Evaluation Boards

Example Application