HPMicro HPM67

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Revision as of 15:46, 22 March 2022 by Erik (talk | contribs) (Dual Core Debugging)
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The HPMicro HPM67xx device series are RISC-V based 32-bit microcontrollers.

SPI flash support

J-Link supports SPI-flashes with HPM67xx through the XPI-API.

Note:
Since the full documentation is currently not available, the flashloader is based on code provided by HPMicro. This currently has the limitation where programming is only supported after reset. Programming and flash breakpoints may work without reset, but it is not guaranteed. In such cases, SEGGER will currently not provide any support.

Dual Core Debugging

The HPM67 family features two cores. CPU0 is the master CPU and CPU1 is the slave CPU. After reset, CPU0 is enabled while CPU1 is in standby. When necessary, the program image of CPU1 is loaded by CPU0, and then CPU1 is released. The steps are as follows:

  1. CPU0 writes the code mirror address of CPU1 into the SYSCTL_CPU1_GPR0 register
  2. CPU0 writes the CPU1 startup code into the SYSCTL_CPU1_GPR1 register, the code is 0xC1BEF1A9
  3. CPU0 clears the SYSCTL_CPU1_LP [HALT] bit to 0 to release CPU1

The J-Link supports debugging of both cores. The desired CPU can be selected via a dedicated device name such as "HPM6758XXXX" for CPU0 and "HPM6758XXXX_CPU1" for CPU1.

Note:
In case of CPU1 is selected, the J-Link performs an attach, only. The J-Link expects that the steps above have been already performed by the application running on CPU0.
For CPU1, no reset is performed by default as this would reset CPU0 as well. If a reset is required, it needs to be added via J-Link script file.

Evaluation Boards