How to implement interrupt handlers for RISC-V
A RISC-V chip can implement a standard interrupt controller with one interrupt handler, or use a vectored interrupt controller where a vector table is used to determine what interrupt to execute.
In this article we will focus on standard interrupt controllers and how Embedded Studio handles them for RISC-V.
The following statements are true for Embedded Studio V6.32a. So it might be that the files and program excerpts look different on other versions, but the working principle is the same.
When generating a generic RISC-V project with the project wizard you will get a simple working "Hello World" project. The Startup of the application happens in file SEGGER_RV32_crt0.s If you look into that file you will find the following code line:
... la a0, trap_entry csrw mtvec, a0 ...
Here the address of trap_entry is loaded into the mtvec register which contains the location of the handler table. So whenever an exception occurs this handler will be called.
You can now either replace this table with your own variant and simply replace the label used here with yours or you overwrite the individual trap handler which is defined as a weak function.
To replace only the trap handler simply implement your own version of function: void handle_trap (void);