Difference between revisions of "IndieSemi Realplum-EVK"

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(→‎Preparing for J-Link)
(→‎Preparing for J-Link)
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== Preparing for J-Link ==
  
== Preparing for J-Link ==
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The SiPeed Longan Nano does not come with a standard debug connector but populates the debug JTAG signals on 6 pads that can be found on the opposite of the USB-C interface. Therefore, it can be manually wired in case J-Link shall be connected to it.
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*Make sure that you install the correct "Upgrade Board"
  
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*Connect the J-Link to the SWD header (P1)
  
   
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The following guide will describe how the Longan Nano Board can be connected to your J-Link Base V10 or higher. Other J-Links might work as well but wiring might be slightly different. All needed information can be found in the probe related documentation.
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FOTO
 
   
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* The Longan Nano board does not come with the pin header populated so first the pin headers need to be soldered to your board.
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*Power the board via external power supply / power jack (J4)
  
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* Now connect the board with e.g. jumperwires to your J-Link probe.
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* The following table shows how the Signals should be connected on both the board and [https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ J-Link] side.
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{| class="wikitable"
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|-
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! J-Link 20 pin debug interface !! Pin on eval board pads
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|-
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| Pin 1 (VTref) || 3V3
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|-
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| Pin 4 (GND) || GND
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|-
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| Pin 5 (TDI) || JTDI
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|-
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| Pin 7 (TMS) || JTMS
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|-
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| Pin 9 (TCK) || JTCK
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|-
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| Pin 13 (TDO) || JTDO
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|-
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|}
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The resulting connection will then look like this:
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[[File:Longan_Nano.png|450px]]
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* Power the board via the USB-C port.
 
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows:
  
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows:
   

Revision as of 15:02, 19 August 2020

This article describes specifics for the IndieSemi Realplum EVK.

TBD NXP JN5189-DK006.jpg

Minimum requirements

  • J-Link software V6.84 or later

Preparing for J-Link

The SiPeed Longan Nano does not come with a standard debug connector but populates the debug JTAG signals on 6 pads that can be found on the opposite of the USB-C interface. Therefore, it can be manually wired in case J-Link shall be connected to it.

The following guide will describe how the Longan Nano Board can be connected to your J-Link Base V10 or higher. Other J-Links might work as well but wiring might be slightly different. All needed information can be found in the probe related documentation.

  • The Longan Nano board does not come with the pin header populated so first the pin headers need to be soldered to your board.
  • Now connect the board with e.g. jumperwires to your J-Link probe.
  • The following table shows how the Signals should be connected on both the board and J-Link side.
J-Link 20 pin debug interface Pin on eval board pads
Pin 1 (VTref) 3V3
Pin 4 (GND) GND
Pin 5 (TDI) JTDI
Pin 7 (TMS) JTMS
Pin 9 (TCK) JTCK
Pin 13 (TDO) JTDO

The resulting connection will then look like this:

Longan Nano.png

  • Power the board via the USB-C port.
  • Verify the Connection with e.g. J-Link Commander. The output should look as follows:

IndieSemi Realplum Connect.PNG

Example Project

The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the IndieSemi Realplum. It is a simple Hello World sample linked into the internal flash. SETUP

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