Difference between revisions of "Infineon CYT2B9"
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− | ! Flash !! Start adress !! End adress !! Sector size !! Sector count !! Total size |
+ | ! Flash !! Start adress !! End adress !! Sector size !! Sector count !! Total size |
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− | | Code flash large area || 0x10000000 || 0x101EFFFF || 32 KiB || 62 || 1984 KiB |
+ | | Code flash large area || 0x10000000 || 0x101EFFFF || 32 KiB || 62 || 1984 KiB |
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− | | Code flash small area || 0x101F0000 || 0x1010FFFF || 8 KiB || 16 || 128 KiB |
+ | | Code flash small area || 0x101F0000 || 0x1010FFFF || 8 KiB || 16 || 128 KiB |
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− | | Work flash large area || 0x14000000 || 0x14017FFF || 2 KiB || 48 || 96 KiB |
+ | | Work flash large area || 0x14000000 || 0x14017FFF || 2 KiB || 48 || 96 KiB |
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− | | Work flash small area || 0x14018000 || 0x1401FFFF || 128 B || 256 || 32 KiB |
+ | | Work flash small area || 0x14018000 || 0x1401FFFF || 128 B || 256 || 32 KiB |
+ | |- |
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+ | | Supervisory flash || 0x17000800 || 0x17007DFF || 512 B || 13|| 6656 B |
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+ | |} |
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+ | |||
+ | == Supervisory Flash == |
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+ | Programming of the supervisory Flash is only at specific areas possible. |
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+ | Writing outside the specific sub-regions is not possible at any Life Cycle stage except VIRGIN which is a factory-only stage. |
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+ | {| class="wikitable" |
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+ | |- |
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+ | ! Address region !! Description |
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+ | |- |
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+ | | 0x17000800-0x17000FFF || The user's area. 2 KB are used to store arbitrary data. |
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+ | |- |
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+ | | 0x17001A00-0x17001A03 || Normal Access Restrictions (NAR). Used for chip protection in the Normal Life Cycle stage. |
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+ | |- |
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+ | | 0x17001A04-0x17001A07 || Normal Dead Access Restrictions (NDAR). Used for chip protection in the Normal Dead Life Cycle stage. |
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+ | |- |
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+ | | 0x17006400-0x17006FFF || The Public Key. Used for a digital signature of the application. |
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+ | |- |
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+ | | 0x17007600-0x170077FF || Application protection settings. |
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+ | |- |
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+ | | 0x17007C00-0x17007DFF || The Table of contents, part 2 (TOC2). Used to locate OEM objects. |
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Revision as of 10:24, 6 July 2022
CYT2B9 (TVII-B-E-2M) is a subfamily of Traveo II microcontrollers containing a Cortex M4 and Cortex M0+ CPU.
SRAM
The CYT2B9 family features 2 x 128 KB = 256 KB of SRAM located at 0x08000000. The first 2 KB are reserved for internal usage and may not be used.
Flash memory layout
The CYT2B9 series devices have 2112 KiB Code flash and a 128 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.
Flash | Start adress | End adress | Sector size | Sector count | Total size |
---|---|---|---|---|---|
Code flash large area | 0x10000000 | 0x101EFFFF | 32 KiB | 62 | 1984 KiB |
Code flash small area | 0x101F0000 | 0x1010FFFF | 8 KiB | 16 | 128 KiB |
Work flash large area | 0x14000000 | 0x14017FFF | 2 KiB | 48 | 96 KiB |
Work flash small area | 0x14018000 | 0x1401FFFF | 128 B | 256 | 32 KiB |
Supervisory flash | 0x17000800 | 0x17007DFF | 512 B | 13 | 6656 B |
Supervisory Flash
Programming of the supervisory Flash is only at specific areas possible. Writing outside the specific sub-regions is not possible at any Life Cycle stage except VIRGIN which is a factory-only stage.
Address region | Description |
---|---|
0x17000800-0x17000FFF | The user's area. 2 KB are used to store arbitrary data. |
0x17001A00-0x17001A03 | Normal Access Restrictions (NAR). Used for chip protection in the Normal Life Cycle stage. |
0x17001A04-0x17001A07 | Normal Dead Access Restrictions (NDAR). Used for chip protection in the Normal Dead Life Cycle stage. |
0x17006400-0x17006FFF | The Public Key. Used for a digital signature of the application. |
0x17007600-0x170077FF | Application protection settings. |
0x17007C00-0x17007DFF | The Table of contents, part 2 (TOC2). Used to locate OEM objects. |