CYT3BB (TVII-B-H-4M) is a subfamily of Traveo II microcontrollers containing a Cortex M7 and Cortex M0+ CPU.
The CYT3BB family features 512 KB + 256 KB = 768 KB of SRAM located at 0x28000000. The first 2 KB are reserved for internal usage and may not be used.
Flash memory layout
The CYT3BB series devices have 4160 KiB Code flash and a 256 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.
|Flash||Start adress||End adress||Sector size||Sector count||Total size|
|Code flash large area||0x10000000||0x103EFFFF||32 KiB||126||4032 KiB|
|Code flash small area||0x103F0000||0x1040FFFF||8 KiB||16||128 KiB|
|Work flash large area||0x14000000||0x1402FFFF||2 KiB||96||192 KiB|
|Work flash small area||0x14030000||0x1403FFFF||128 B||512||64 KiB|