Infineon CYT4BB

CYT4BB (TVII-B-H-4M) is a subfamily of Traveo II microcontrollers containing a Cortex M7 and Cortex M0+ CPU.

SRAM

The CYT4BB family features 512 KB + 256 KB = 768 KB of SRAM located at 0x28000000. The first 2 KB are reserved for internal usage and may not be used.

Flash memory layout

The CYT4BB series devices have 4160 KiB Code flash and a 256 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.

Flash	Start adress	End adress	Sector size	Sector count	Total size
Code flash large area	0x10000000	0x103EFFFF	32 KiB	126	4032 KiB
Code flash small area	0x103F0000	0x1040FFFF	8 KiB	16	128 KiB
Work flash large area	0x14000000	0x1402FFFF	2 KiB	96	192 KiB
Work flash small area	0x14030000	0x1403FFFF	128 B	512	64 KiB
Supervisory flash	0x17000800	0x17007DFF	512 B	13	6656 B

Supervisory Flash

Programming of the supervisory Flash is only at specific areas possible. Writing outside the specific sub-regions is not possible at any Life Cycle stage except VIRGIN which is a factory-only stage.

Address region	Description
0x17000800-0x17000FFF	The user's area. 2 KB are used to store arbitrary data.
0x17001A00-0x17001A03	Normal Access Restrictions (NAR). Used for chip protection in the Normal Life Cycle stage.
0x17001A04-0x17001A07	Normal Dead Access Restrictions (NDAR). Used for chip protection in the Normal Dead Life Cycle stage.
0x17006400-0x17006FFF	The Public Key. Used for a digital signature of the application.
0x17007600-0x170077FF	Application protection settings.
0x17007C00-0x17007DFF	The Table of contents, part 2 (TOC2). Used to locate OEM objects.