Difference between revisions of "Infineon Traveo T2G"

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(Sub families)
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* [[Cypress CYT4BB‎]]
 
* [[Cypress CYT4BB‎]]
 
* [[Cypress CYT4BF‎]]
 
* [[Cypress CYT4BF‎]]
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== FAQ ==
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(Q1) What is the expected method for IDE to connect with M0 core and M4 or M7 core?
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For M0 no special handling is needed. For M4 and M7 core avoid resets before connecting to the core as this might disable M4/M7 core.
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(Q2) Is it possible to connect CYT2B63BAD_M4 only from J-Link Commander without connection to CYT2B63BAD_M0?
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Yes connecting directly to M4/M7 is possible, as during our connect sequence J-Link connects to the M0 to enable M4/M7 core before connecting to M4/M7.

Revision as of 16:34, 10 August 2021

This article describes device specifics of the Cypress Traveo II device family.

Read Work Flash

Reading from work flash that is still in erased state will result in an error message, because of the nature of differential flash. Normal usage of work flash is as follows:

  1. Erase entire sector.
  2. Program word(s).
  3. Read 32-bit word.

Flash breakpoints

For Cypress Traveo II series devices the flash breakpoint feature may lead to hard-faults. This is due to the reason that it is mandatory to activate interrupts for flash programming on these devices. As a result interrupts like Systick timer can disrupt the flash programming routine and try to access flash areas themselves, which can lead to hard-faults.

Flash programming with M4 core

Currently, when using the Cortex-M4, flash programming with J-Flash is not possible. Programming with the J-Link Commander utility is however possible.

Sub families

The Traveo II device family has the following sub families:

FAQ

(Q1) What is the expected method for IDE to connect with M0 core and M4 or M7 core?

For M0 no special handling is needed. For M4 and M7 core avoid resets before connecting to the core as this might disable M4/M7 core.

(Q2) Is it possible to connect CYT2B63BAD_M4 only from J-Link Commander without connection to CYT2B63BAD_M0?

Yes connecting directly to M4/M7 is possible, as during our connect sequence J-Link connects to the M0 to enable M4/M7 core before connecting to M4/M7.