Difference between revisions of "J-Link EDU Mini V1"

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(→‎Supported cores)
 
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__TOC__
  
__TOC__
   
−
== Hardware and Software Features ==
 +
== Hardware Features ==
−
{| class="wikitable"
 +
{| class="seggertable"
−
|+
  
 
|-
  
|-
  +
! Feature !! Supported
−
! style="position:sticky; top:0"|Hardware version
  
−
! style="position:sticky; top:0"|1
  
−
|- style="text-align:center"
  
−
|colspan="7"| Hardware Features
  
 
|-
  
|-
−
! style="text-align:left;"|USB 2.0 Full Speed || {{YES}}
 +
|| USB 2.0 Full Speed ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|USB 2.0 Hi-Speed || {{NO}}
 +
|| USB 2.0 Hi-Speed ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|JTAG interface || {{YES}}
 +
|| JTAG interface ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|cJTAG interface || {{YES}}
 +
|| cJTAG interface ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SWD interface || {{YES}}
 +
|| cJTAG interface without/buggy KEEPER logic ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SWO interface || {{YES}}
 +
|| SWD interface ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SPI interface || {{NO}}
 +
|| SWO interface ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|QSPI interface || {{NO}}
 +
|| SPI interface ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Microchip ICSP interface || {{NO}}
 +
|| QSPI interface ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Renesas FINE interface || {{NO}}
 +
|| Microchip ICSP interface ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|SiLabs C2 2-wire interface || {{NO}}
 +
|| Renesas FINE interface ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|ETB Trace ARM7/9 || {{NO}}
 +
|| SiLabs C2 2-wire interface ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|ETB Trace Cortex-M || {{YES}}
 +
|| ETB Trace ARM7/9 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|ETB Trace Cortex-A/R || {{NO}}
 +
|| ETB Trace Cortex-M ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|ETM Trace Cortex-M || {{NO}}
 +
|| ETB Trace Cortex-A/R ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|VCOM || {{NO}}
 +
|| ETM Trace Cortex-M ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Memory Stop mode support || {{YES}}
 +
|| VCOM ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M Monitor Mode debugging || {{NO}}
 +
|| Memory Stop mode support ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SWD Multi-Drop || {{NO}}
 +
|| Cortex-M Monitor Mode debugging ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|CMSIS-DAP mode || {{NO}}
 +
|| SWD Multi-Drop ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
|- style="text-align:center"
 +
|| CMSIS-DAP mode ||style="text-align:center;"| {{NO}}
  +
|}
−
|colspan="7"| ARM legacy Cores
  
  +
  +
== Supported cores ==
  +
J-Link provides debugging support for the following cores.<br>
  +
{{Note|1=If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the [https://www.segger.com/ticket SEGGER support ticket system].}}
  +
  +
{| class="seggertable"
 
|-
  
|-
  +
! Core !! Supported
−
! style="text-align:left;"|ARM7 || {{NO}}
  
 
|-
  
|-
  +
!colspan="2"| ARM legacy Cores
−
! style="text-align:left;"|ARM9 || {{NO}}
  
 
|-
  
|-
−
! style="text-align:left;"|ARM11 || {{NO}}
 +
|| ARM7 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
|- style="text-align:center"
 +
|| ARM9 ||style="text-align:center;"| {{NO}}
−
|colspan="7"| ARM Cortex Cores
  
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A5 || {{YES}}
 +
|| ARM11 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A7 || {{YES}}
 +
!colspan="2"| ARM Cortex Cores
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A8 || {{YES}}
 +
|| Cortex-A5 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A9 || {{YES}}
 +
|| Cortex-A7 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A12 || {{YES}}
 +
|| Cortex-A8 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A15 || {{YES}}
 +
|| Cortex-A9 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A17 || {{YES}}
 +
|| Cortex-A12 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A53 || {{NO}}
 +
|| Cortex-A15 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A57 || {{NO}}
 +
|| Cortex-A17 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A72 || {{NO}}
 +
|| Cortex-A53 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M0 || {{YES}}
 +
|| Cortex-A55 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M0+ || {{YES}}
 +
|| Cortex-A57 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M1 || {{YES}}
 +
|| Cortex-A72 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M3 || {{YES}}
 +
|| Cortex-M0 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M4 || {{YES}}
 +
|| Cortex-M0+ ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M7 || {{YES}}
 +
|| Cortex-M1 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M23 || {{YES}}
 +
|| Cortex-M3 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M33 || {{YES}}
 +
|| Cortex-M4 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M85 || {{YES}}
 +
|| Cortex-M7 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-R4 || {{YES}}
 +
|| Cortex-M23 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-R5 || {{YES}}
 +
|| Cortex-M33 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-R8 || {{YES}}
 +
|| Cortex-M85 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SC000 (M0 secure) || {{YES}}
 +
|| Cortex-R4 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SC300 (M3 secure) || {{YES}}
 +
|| Cortex-R5 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
|- style="text-align:center"
 +
|| Cortex-R8 ||style="text-align:center;"| {{YES}}
−
|colspan="7"| RISC-V
  
 
|-
  
|-
−
! style="text-align:left;"|RV32 || {{YES}}
 +
|| SC000 (M0 secure) ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|RV64 || {{YES}}
 +
|| SC300 (M3 secure) ||style="text-align:center;"| {{YES}}
 
|-
  
|-
  +
!colspan="2"| RISC-V
−
|- style="text-align:center"
  
−
|colspan="7"| Microchip PIC32
  
 
|-
  
|-
−
! style="text-align:left;"|PIC32MX || {{NO}}
 +
|| RV32 ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|PIC32MZ || {{NO}}
 +
|| RV64 ||style="text-align:center;"| {{YES}}
−
|- style="text-align:center"
  
−
|colspan="7"| SiLabs 8051
  
 
|-
  
|-
  +
!colspan="2"| Microchip PIC32
−
! style="text-align:left;"|EFM8 || {{NO}}
  
 
|-
  
|-
−
|- style="text-align:center"
 +
|| PIC32MX ||style="text-align:center;"| {{NO}}
−
|colspan="7"| Renesas RX
  
 
|-
  
|-
−
! style="text-align:left;"|RX110 || {{NO}}
 +
|| PIC32MZ ||style="text-align:center;"| {{NO}}
 
|-
  
|-
  +
!colspan="2"| SiLabs 8051
−
! style="text-align:left;"|RX111 || {{NO}}
  
 
|-
  
|-
−
! style="text-align:left;"|RX210 || {{NO}}
 +
|| EFM8 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
  +
!colspan="2"| Renesas RX
−
! style="text-align:left;"|RX21A || {{NO}}
  
 
|-
  
|-
−
! style="text-align:left;"|RX220 || {{NO}}
 +
|| RX110 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX610 || {{NO}}
 +
|| RX111 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX621 || {{NO}}
 +
|| RX140 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX62G || {{NO}}
 +
|| RX210 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX62G || {{NO}}
 +
|| RX21A ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX62N || {{NO}}
 +
|| RX220 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX62T || {{NO}}
 +
|| RX610 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX630 || {{NO}}
 +
|| RX621 ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX631 || {{NO}}
 +
|| RX62G ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX63N || {{NO}}
 +
|| RX62G ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX63T || {{NO}}
 +
|| RX62N ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX64M || {{NO}}
 +
|| RX62T ||style="text-align:center;"| {{NO}}
  +
|-
  +
|| RX630 ||style="text-align:center;"| {{NO}}
  +
|-
  +
|| RX631 ||style="text-align:center;"| {{NO}}
  +
|-
  +
|| RX63N ||style="text-align:center;"| {{NO}}
  +
|-
  +
|| RX63T ||style="text-align:center;"| {{NO}}
  +
|-
  +
|| RX64M ||style="text-align:center;"| {{NO}}
  +
|-
  +
|| RX660 ||style="text-align:center;"| {{NO}}
 
|}
  
|}

Latest revision as of 17:41, 30 October 2023

This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Link EDU Mini V1.

Hardware Features

Feature Supported
USB 2.0 Full Speed YES.png
USB 2.0 Hi-Speed NO.png
JTAG interface YES.png
cJTAG interface YES.png
cJTAG interface without/buggy KEEPER logic YES.png
SWD interface YES.png
SWO interface YES.png
SPI interface NO.png
QSPI interface NO.png
Microchip ICSP interface NO.png
Renesas FINE interface NO.png
SiLabs C2 2-wire interface NO.png
ETB Trace ARM7/9 NO.png
ETB Trace Cortex-M YES.png
ETB Trace Cortex-A/R NO.png
ETM Trace Cortex-M NO.png
VCOM NO.png
Memory Stop mode support YES.png
Cortex-M Monitor Mode debugging NO.png
SWD Multi-Drop NO.png
CMSIS-DAP mode NO.png

Supported cores

J-Link provides debugging support for the following cores.

Note:
If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
Core Supported
ARM legacy Cores
ARM7 NO.png
ARM9 NO.png
ARM11 NO.png
ARM Cortex Cores
Cortex-A5 YES.png
Cortex-A7 YES.png
Cortex-A8 YES.png
Cortex-A9 YES.png
Cortex-A12 YES.png
Cortex-A15 YES.png
Cortex-A17 YES.png
Cortex-A53 YES.png
Cortex-A55 YES.png
Cortex-A57 YES.png
Cortex-A72 YES.png
Cortex-M0 YES.png
Cortex-M0+ YES.png
Cortex-M1 YES.png
Cortex-M3 YES.png
Cortex-M4 YES.png
Cortex-M7 YES.png
Cortex-M23 YES.png
Cortex-M33 YES.png
Cortex-M85 YES.png
Cortex-R4 YES.png
Cortex-R5 YES.png
Cortex-R8 YES.png
SC000 (M0 secure) YES.png
SC300 (M3 secure) YES.png
RISC-V
RV32 YES.png
RV64 YES.png
Microchip PIC32
PIC32MX NO.png
PIC32MZ NO.png
SiLabs 8051
EFM8 NO.png
Renesas RX
RX110 NO.png
RX111 NO.png
RX140 NO.png
RX210 NO.png
RX21A NO.png
RX220 NO.png
RX610 NO.png
RX621 NO.png
RX62G NO.png
RX62G NO.png
RX62N NO.png
RX62T NO.png
RX630 NO.png
RX631 NO.png
RX63N NO.png
RX63T NO.png
RX64M NO.png
RX660 NO.png
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