Difference between revisions of "J-Link PLUS V11"
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== Hardware and Software Features == |
== Hardware and Software Features == |
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{| class="wikitable" |
{| class="wikitable" |
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− | !colspan="8"| Hardware Features |
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+ | ! style="position:sticky; top:0"|Hardware version |
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− | | USB 2.0 Full Speed || {{YES}} |
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+ | ! style="position:sticky; top:0"|11 |
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− | |- |
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+ | |- style="text-align:center" |
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− | | USB 2.0 Hi-Speed || {{YES}} |
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+ | |colspan="8"| Hardware Features |
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+ | ! style="text-align:left;"|USB 2.0 Full Speed || {{YES}} |
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− | | JTAG interface || {{YES}} |
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+ | ! style="text-align:left;"|USB 2.0 Hi-Speed || {{YES}} |
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− | | cJTAG interface || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|JTAG interface || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|cJTAG interface || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|SWD interface || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|SWO interface || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|SPI interface || {{YES}} |
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+ | ! style="text-align:left;"|QSPI interface || {{NO}} |
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+ | ! style="text-align:left;"|Microchip ICSP interface || {{YES}} |
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+ | ! style="text-align:left;"|Renesas FINE interface || {{YES}} |
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− | | ETB Trace ARM7/9 || {{YES}} |
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+ | ! style="text-align:left;"|SiLabs C2 2-wire interface || {{YES}} |
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− | | ETB Trace Cortex-M || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|ETB Trace ARM7/9 || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|ETB Trace Cortex-M || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|ETB Trace Cortex-A/R || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|ETM Trace Cortex-M || {{NO}} |
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− | + | ! style="text-align:left;"|VCOM || {{YES}} |
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− | + | ! style="text-align:left;"|Memory Stop mode support || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-M Monitor Mode debugging || {{NO}} |
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− | | CMSIS-DAP mode || {{YES}} |
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+ | ! style="text-align:left;"|SWD Multi-Drop || {{YES}} |
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− | ! colspan="8"| ARM legacy Cores |
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+ | ! style="text-align:left;"|CMSIS-DAP mode || {{YES}} |
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+ | |- style="text-align:center" |
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− | | ARM9 || {{YES}} |
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+ | |colspan="7"| ARM legacy Cores |
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− | + | ! style="text-align:left;"|ARM7 || {{YES}} |
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+ | ! style="text-align:left;"|ARM9 || {{YES}} |
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− | ! colspan="8"| ARM Cortex Cores |
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− | + | ! style="text-align:left;"|ARM11 || {{YES}} |
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+ | |- style="text-align:center" |
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− | | Cortex-A7 || {{YES}} |
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+ | |colspan="7"| ARM Cortex Cores |
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− | + | ! style="text-align:left;"|Cortex-A5 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A7 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A8 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A9 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A12 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A15 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A17 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A53 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-A57 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-A72 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-M0 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-M0+ || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-M1 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-M3 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-M4 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-M7 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-M23 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-M33 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-R4 || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-R5 || {{YES}} |
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− | | SC000 (M0 secure) || {{YES}} |
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+ | ! style="text-align:left;"|Cortex-R8 || {{YES}} |
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− | | SC300 (M3 secure) || {{YES}} |
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+ | ! style="text-align:left;"|SC000 (M0 secure) || {{YES}} |
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− | ! colspan="8"| RISC-V |
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+ | ! style="text-align:left;"|SC300 (M3 secure) || {{YES}} |
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− | | RV32 || {{YES}} |
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+ | |- style="text-align:center" |
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− | | RV64 || {{YES}} |
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+ | |colspan="7"| RISC-V |
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+ | ! style="text-align:left;"|RV32 || {{YES}} |
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− | ! colspan="8"| Microchip PIC32 |
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+ | ! style="text-align:left;"|RV64 || {{YES}} |
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− | | PIC32MX || {{YES}} |
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+ | |- style="text-align:center" |
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− | | PIC32MZ || {{YES}} |
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+ | |colspan="7"| Microchip PIC32 |
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+ | ! style="text-align:left;"|PIC32MX || {{YES}} |
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− | ! colspan="8" | SiLabs 8051 |
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+ | ! style="text-align:left;"|PIC32MZ || {{YES}} |
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− | | EFM8 || {{YES}} |
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+ | |- style="text-align:center" |
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+ | |colspan="7"| SiLabs 8051 |
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+ | ! style="text-align:left;"|EFM8 || {{YES}} |
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− | ! colspan="8"| Renesas RX |
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+ | |- style="text-align:center" |
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− | | RX110 || {{YES}} |
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+ | |colspan="7"| Renesas RX |
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+ | ! style="text-align:left;"|RX110 || {{YES}} |
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− | | RX111 || {{YES}} |
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+ | ! style="text-align:left;"|RX111 || {{YES}} |
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− | | RX210 || {{YES}} |
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+ | ! style="text-align:left;"|RX210 || {{YES}} |
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− | | RX21A || {{YES}} |
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+ | ! style="text-align:left;"|RX21A || {{YES}} |
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− | | RX220 || {{YES}} |
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+ | ! style="text-align:left;"|RX220 || {{YES}} |
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− | | RX610 || {{YES}} |
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+ | ! style="text-align:left;"|RX610 || {{YES}} |
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− | | RX621 || {{YES}} |
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+ | ! style="text-align:left;"|RX621 || {{YES}} |
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− | | RX62G || {{YES}} |
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− | | |
+ | ! style="text-align:left;"|RX62G || {{YES}} |
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+ | ! style="text-align:left;"|RX62G || {{YES}} |
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− | | RX62N || {{YES}} |
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+ | ! style="text-align:left;"|RX62N || {{YES}} |
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− | | RX62T || {{YES}} |
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+ | ! style="text-align:left;"|RX62T || {{YES}} |
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− | | RX630 || {{YES}} |
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+ | ! style="text-align:left;"|RX630 || {{YES}} |
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− | | RX631 || {{YES}} |
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+ | ! style="text-align:left;"|RX631 || {{YES}} |
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− | | RX63N || {{YES}} |
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+ | ! style="text-align:left;"|RX63N || {{YES}} |
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− | | RX63T || {{YES}} |
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+ | ! style="text-align:left;"|RX63T || {{YES}} |
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− | | RX64M || {{YES}} |
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+ | |- |
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+ | ! style="text-align:left;"|RX64M || {{YES}} |
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Revision as of 18:12, 9 December 2021
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Link PLUS V11.
Hardware and Software Features
Hardware version | 11 | ||||||
---|---|---|---|---|---|---|---|
Hardware Features | |||||||
USB 2.0 Full Speed | |||||||
USB 2.0 Hi-Speed | |||||||
JTAG interface | |||||||
cJTAG interface | |||||||
SWD interface | |||||||
SWO interface | |||||||
SPI interface | |||||||
QSPI interface | |||||||
Microchip ICSP interface | |||||||
Renesas FINE interface | |||||||
SiLabs C2 2-wire interface | |||||||
ETB Trace ARM7/9 | |||||||
ETB Trace Cortex-M | |||||||
ETB Trace Cortex-A/R | |||||||
ETM Trace Cortex-M | |||||||
VCOM | |||||||
Memory Stop mode support | |||||||
Cortex-M Monitor Mode debugging | |||||||
SWD Multi-Drop | |||||||
CMSIS-DAP mode | |||||||
ARM legacy Cores | |||||||
ARM7 | |||||||
ARM9 | |||||||
ARM11 | |||||||
ARM Cortex Cores | |||||||
Cortex-A5 | |||||||
Cortex-A7 | |||||||
Cortex-A8 | |||||||
Cortex-A9 | |||||||
Cortex-A12 | |||||||
Cortex-A15 | |||||||
Cortex-A17 | |||||||
Cortex-A53 | |||||||
Cortex-A57 | |||||||
Cortex-A72 | |||||||
Cortex-M0 | |||||||
Cortex-M0+ | |||||||
Cortex-M1 | |||||||
Cortex-M3 | |||||||
Cortex-M4 | |||||||
Cortex-M7 | |||||||
Cortex-M23 | |||||||
Cortex-M33 | |||||||
Cortex-R4 | |||||||
Cortex-R5 | |||||||
Cortex-R8 | |||||||
SC000 (M0 secure) | |||||||
SC300 (M3 secure) | |||||||
RISC-V | |||||||
RV32 | |||||||
RV64 | |||||||
Microchip PIC32 | |||||||
PIC32MX | |||||||
PIC32MZ | |||||||
SiLabs 8051 | |||||||
EFM8 | |||||||
Renesas RX | |||||||
RX110 | |||||||
RX111 | |||||||
RX210 | |||||||
RX21A | |||||||
RX220 | |||||||
RX610 | |||||||
RX621 | |||||||
RX62G | |||||||
RX62G | |||||||
RX62N | |||||||
RX62T | |||||||
RX630 | |||||||
RX631 | |||||||
RX63N | |||||||
RX63T | |||||||
RX64M |
Specifications
Specification | Value |
---|---|
General | |
Supported OS | Microsoft Windows (x86/x64), Linux (x86/x64/Arm), macOS (x86) |
Electromagnetic compatibility (EMC) | EN 55022, EN 55024 |
Operating temperature | +5°C ... +60°C |
Storage temperature | -20°C ... +65 °C |
Relative humidity (non-condensing) | Max. 90% rH |
Mechanical | |
Size (without cables) | 100mm x 53mm x 27mm |
Weight (without cables) | 70g |
Available interfaces | |
USB interface | USB 2.0 (Hi-Speed); USB Type B |
Target interface | JTAG 20-pin (14-pin and other adapters available) |
JTAG/SWD Interface, Electrical | |
Power supply | USB powered Max. 50mA + Target Supply current. |
Target interface voltage (VIF) | 1.2V ... 5V |
Target supply voltage | 5V (derived from USB voltage) |
Target supply current | Max. 300mA |
Reset Type | Open drain. Can be pulled low or tristated. |
Reset low level output voltage (VOL) | VOL <= 10% of VIF |
For the whole target voltage range (1.2V <= VIF <= 5V) | |
LOW level input voltage (VIL) | VIL <= 40% of VIF |
HIGH level input voltage (VIH) | VIH >= 60% of VIF |
For 1.2V <= VIF <= 3.6V | |
LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
For 3.6 <= VIF <= 5V | |
LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
JTAG/SWD Interface, Timing | |
Target interface speed | Max. 15 MHz |
SWO sampling frequency | Max. 30 MHz |
Data input rise time (Trdi) | Trdi <= 20ns |
Data input fall time (Tfdi) | Tfdi <= 20ns |
Data output rise time (Trdo) | Trdo <= 10ns |
Data output fall time (Tfdo) | Tfdo <= 10ns |
Clock rise time (Trc) | Trc <= 3ns |
Clock fall time (Tfc) | Tfc <= 3ns |