Difference between revisions of "J-Link SiFive Insight"

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(Supported implementations)
 
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= Supported implementations =
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== Supported implementations ==
 
The following implementations are currently supported:
 
The following implementations are currently supported:
   
  +
=== J-Link ===
 
* Trace encoder module + SRAM sink
 
* Trace encoder module + SRAM sink
* With the [https://www.segger.com/products/debug-probes/j-trace/models/j-trace-pro-risc-v/ J-Trace Pro RISC-V] streaming trace via trace pins is also supported
 
   
  +
=== J-Trace Pro RISC-V ===
= Min. required version =
 
  +
* Trace encoder module + SRAM sink
SiFive Insight trace is supported for J-Link software version V6.65b and later.
 
  +
* Trace encoder module + trace pin sink
  +
  +
  +
== Min. required version ==
  +
SiFive Insight trace is supported for J-Link software version V6.65b and later for J-Link and V7.80b or later for J-Trace Pro RISC-V.
   
= Example projects =
+
== Example projects ==
 
SiFive provides a E31 bitstream for the ARTY-100T board that incorporates SiFive Insight trace.
 
SiFive provides a E31 bitstream for the ARTY-100T board that incorporates SiFive Insight trace.
   

Latest revision as of 09:59, 7 October 2022

SiFive Insight is a Nexus based IP and protocol to enable tracing on their RISC-V cores. SiFive Insight is supported by J-Link and J-Trace Pro RISC-V.

Supported implementations

The following implementations are currently supported:

J-Link

  • Trace encoder module + SRAM sink

J-Trace Pro RISC-V

  • Trace encoder module + SRAM sink
  • Trace encoder module + trace pin sink


Min. required version

SiFive Insight trace is supported for J-Link software version V6.65b and later for J-Link and V7.80b or later for J-Trace Pro RISC-V.

Example projects

SiFive provides a E31 bitstream for the ARTY-100T board that incorporates SiFive Insight trace.