Difference between revisions of "J-Link ULTRA+ V4"
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| + | #REDIRECT [[J-Link ULTRA V4]] |
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| − | This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER '''J-Link UTLRA V4'''. |
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| − | |||
| − | {{DisclaimerLegacyJLink|J-Link UTLRA V4}} |
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| − | |||
| − | <br> |
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| − | __TOC__ |
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| − | == Hardware and Software Features == |
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| − | {| class="wikitable" |
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| − | |+ |
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| − | |- |
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| − | |- style="text-align:center" |
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| − | |colspan="8"| Hardware Features |
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| − | |- |
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| − | ! style="text-align:left;"|USB 2.0 Full Speed || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|USB 2.0 Hi-Speed || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|JTAG interface || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|cJTAG interface || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|SWD interface || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|SWO interface || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|SPI interface || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|QSPI interface || {{NO}} |
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| − | |- |
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| − | ! style="text-align:left;"|Microchip ICSP interface || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Renesas FINE interface || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|SiLabs C2 2-wire interface || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|ETB Trace ARM7/9 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|ETB Trace Cortex-M || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|ETB Trace Cortex-A/R || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|ETM Trace Cortex-M || {{NO}} |
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| − | |- |
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| − | ! style="text-align:left;"|VCOM || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Memory Stop mode support || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-M Monitor Mode debugging || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|SWD Multi-Drop || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|CMSIS-DAP mode || {{NO}} |
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| − | |- |
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| − | |- style="text-align:center" |
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| − | |colspan="7"| ARM legacy Cores |
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| − | |- |
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| − | ! style="text-align:left;"|ARM7 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|ARM9 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|ARM11 || {{YES}} |
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| − | |- |
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| − | |- style="text-align:center" |
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| − | |colspan="7"| ARM Cortex Cores |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A5 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A7 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A8 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A9 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A12 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A15 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A17 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A53 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A57 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-A72 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-M0 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-M0+ || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-M1 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-M3 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-M4 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-M7 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-M23 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-M33 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-R4 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-R5 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|Cortex-R8 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|SC000 (M0 secure) || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|SC300 (M3 secure) || {{YES}} |
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| − | |- |
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| − | |- style="text-align:center" |
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| − | |colspan="7"| RISC-V |
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| − | |- |
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| − | ! style="text-align:left;"|RV32 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RV64 || {{YES}} |
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| − | |- |
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| − | |- style="text-align:center" |
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| − | |colspan="7"| Microchip PIC32 |
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| − | |- |
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| − | ! style="text-align:left;"|PIC32MX || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|PIC32MZ || {{YES}} |
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| − | |- |
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| − | |- style="text-align:center" |
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| − | |colspan="7"| SiLabs 8051 |
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| − | |- |
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| − | ! style="text-align:left;"|EFM8 || {{YES}} |
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| − | |- |
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| − | |- style="text-align:center" |
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| − | |colspan="7"| Renesas RX |
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| − | |- |
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| − | ! style="text-align:left;"|RX110 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX111 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX210 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX21A || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX220 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX610 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX621 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX62G || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX62G || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX62N || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX62T || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX630 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX631 || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX63N || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX63T || {{YES}} |
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| − | |- |
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| − | ! style="text-align:left;"|RX64M || {{YES}} |
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| − | |} |
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Latest revision as of 18:39, 7 February 2022
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